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* [XRay] Refactor file header reading (NFC)Dean Michael Berris2018-08-221-0/+33
* [AST] Move a function definition into the cpp [NFC]Philip Reames2018-08-221-11/+1
* Update MemorySSA in BasicBlockUtils.Alina Sbirlea2018-08-211-11/+16
* [MemorySSA] Update comment for move APIs to clarify behavior (NFC).Alina Sbirlea2018-08-211-11/+11
* MachineScheduler: Refactor setPolicy() to limit computing remaining latencyTom Stellard2018-08-211-0/+4
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-214-0/+14
* Fix Wdocumentation warning. NFCI.Simon Pilgrim2018-08-211-1/+1
* [AST] Remove notion of volatile from alias sets [NFCI]Philip Reames2018-08-211-9/+1
* Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit coun...Aditya Nandakumar2018-08-213-0/+17
* AMDGPU: Partially move target handling code from clang to TargetParserMatt Arsenault2018-08-211-0/+80
* [AMDGPU] Allow int types for MUBUF vdataTim Renouf2018-08-211-4/+4
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-211-0/+117
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-211-0/+49
* [llvm] NFC: Fix assert condition and suppress warningKirill Bobyrev2018-08-211-1/+1
* [NFC] Factor out predecessors collection into a separate methodMax Kazantsev2018-08-211-0/+7
* [WebAssembly] Revert type of wake count in atomic.wake to i32Heejin Ahn2018-08-201-1/+1
* Move Itanium demangler implementation into a header file and add visitation s...Richard Smith2018-08-204-0/+5484
* [FPEnv] Support constrained FREM intrinsicCameron McInally2018-08-201-0/+1
* [PSV] Update API to be able to use TargetCustom without UB.Marcello Maggioni2018-08-202-6/+6
* Revert "Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics"Aditya Nandakumar2018-08-202-0/+21
* [MemorySSA] Update comment to better describe cfg change (NFC).Alina Sbirlea2018-08-201-3/+3
* Revert rr340111 "[GISel]: Add Legalization/lowering code for bit counting ope...Reid Kleckner2018-08-203-17/+0
* Add cmake option to disable minidumps, default it to offReid Kleckner2018-08-201-0/+3
* [DWARF] Refactor DWARF classes to use unified error reporting. NFC.Victor Leschuk2018-08-201-6/+5
* [llvm] Make YAML serialization up to 2.5 times fasterKirill Bobyrev2018-08-201-27/+82
* [LLVM-C] Add coroutine passeswhitequark2018-08-191-0/+55
* [C-API][DIBuilder] Added DIFlags in LLVMDIBuilderCreateBasicTypewhitequark2018-08-191-1/+5
* Add the extended XMM registers mappings for AVX-512.Zachary Turner2018-08-181-0/+17
* [ORC] Fix some parameter names. NFC.Lang Hames2018-08-181-4/+4
* [ORC] Rename 'finalize' to 'emit' to avoid potential confusion.Lang Hames2018-08-182-19/+26
* [GISel]: Add Legalization/lowering code for bit counting operationsAditya Nandakumar2018-08-183-0/+17
* [ORC] Rename VSO to JITDylib.Lang Hames2018-08-176-147/+158
* [AST] Adapt Polly to AnalysisSetTracker changes. NFC.Michael Kruse2018-08-171-7/+0
* [IDF] Make GD const.Alina Sbirlea2018-08-171-1/+1
* [Support] NFC: Fix docstring in FileSystem.h.Reka Kovacs2018-08-171-1/+1
* [InstCombine] Refactor the simplification of pow() (NFC)Evandro Menezes2018-08-171-0/+1
* [IDF] Teach Iterated Dominance Frontier to use a snapshot CFG based on a Grap...Alina Sbirlea2018-08-171-10/+16
* [ThinLTO] Add option for printing import failure reasonsTeresa Johnson2018-08-172-1/+61
* [DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)Hsiangkai Wang2018-08-171-0/+4
* [InstrSimplify,NewGVN] Add option to ignore additional instr info when simpli...Florian Hahn2018-08-172-19/+74
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-173-0/+4
* [MISC]Fix wrong usage of std::equal()Chen Zheng2018-08-171-12/+21
* [MustExecute] Fix algorithmic bug in isGuaranteedToExecute. PR38514Max Kazantsev2018-08-171-0/+6
* Revert r339977: [GISel]: Add Opcodes for a few LLVM IntrinsicsChandler Carruth2018-08-172-21/+0
* [Support] Add a public API to allow clearing all (static) timer groups.Graydon Hoare2018-08-171-3/+11
* [GISel]: Add Opcodes for a few LLVM IntrinsicsAditya Nandakumar2018-08-172-0/+21
* [ADT] Replace a member initializer of a union with an explicitChandler Carruth2018-08-171-2/+6
* [x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth2018-08-161-6/+8
* [InstrProf] Use atomic profile counter updates for TSanVedant Kumar2018-08-161-0/+3
* Update MemorySSA in Local utils removing blocks.Alina Sbirlea2018-08-161-4/+7
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