summaryrefslogtreecommitdiffstats
path: root/llvm/include/llvm/BinaryFormat/ELFRelocs
Commit message (Collapse)AuthorAgeFilesLines
* [ELF][PowerPC] Support R_PPC_COPY and R_PPC64_COPYFangrui Song2020-01-241-0/+2
| | | | | | | | Reviewed By: Bdragon28, jhenderson, grimar, sfertile Differential Revision: https://reviews.llvm.org/D73255 (cherry picked from commit f1dab29908d25a4044abff6ffc120c48b20f034d)
* [AARCH64] Switch relocations R_AARCH64_TLS_TPREL64 and R_AARCH64_DTPMOD64Peter Smith2019-07-311-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ELF for the Arm 64-bit Architecture document originally specified R_AARCH64_TLS_DTPREL64 = 0x404 R_AARCH64_TLS_DTPMOD64 = 0x405 LLVM correctly followed the document. Unfortunately in binutils these two codes were reversed: R_AARCH64_TLS_DTPMOD64 = 0x404 R_AARCH64_TLS_DTPREL64 = 0x405 Given that binaries had shipped this change has become the defacto standard interpretation of these relocation codes for any toolchain that wanted to remain compatible with GNU. To recognize this the latest version of the ABI document has renamed the relocations to R_AARCH64_TLS_IMPDEF1 and R_AARCH64_TLS_IMPDEF2 permitting a toolchain to choose between the two relocation types, and recommending that toolchains follow the GNU interpretation for maximum compatibility. Given that upstream llvm has never implemented the standard TLS model for AArch64 so we have no binary legacy, synchronize with GCC so that we don't create incompatible objects in the future. So far the only visible change is in llvm-readobj as it can decode these relocations. Tthis change will mean that llvm-readobj decodes the same way as GNU readelf. fixes PR40507 llvm-svn: 367437
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the new family of conditional selection / increment / negation instructions; the low-overhead branch instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole list of registers at once; the new VMRS/VMSR and VLDR/VSTR instructions to get data in and out of 8.1-M system registers, particularly including the new VPR register used by MVE vector predication. To support this, we also add a register name 'zr' (used by the CSEL family to force one of the inputs to the constant 0), and operand types for lists of registers that are also allowed to include APSR or VPR (used by CLRM). The VLDR/VSTR instructions also need a new addressing mode. The low-overhead branch instructions exist in their own separate architecture extension, which we treat as enabled by default, but you can say -mattr=-lob or equivalent to turn it off. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Reviewed By: samparker Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62667 llvm-svn: 363039
* Revert rL362953 and its followup rL362955.Simon Tatham2019-06-101-3/+0
| | | | | | | | These caused a build failure because I managed not to notice they depended on a later unpushed commit in my current stack. Sorry about that. llvm-svn: 362956
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the new family of conditional selection / increment / negation instructions; the low-overhead branch instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole list of registers at once; the new VMRS/VMSR and VLDR/VSTR instructions to get data in and out of 8.1-M system registers, particularly including the new VPR register used by MVE vector predication. To support this, we also add a register name 'zr' (used by the CSEL family to force one of the inputs to the constant 0), and operand types for lists of registers that are also allowed to include APSR or VPR (used by CLRM). The VLDR/VSTR instructions also need some new addressing modes. The low-overhead branch instructions exist in their own separate architecture extension, which we treat as enabled by default, but you can say -mattr=-lob or equivalent to turn it off. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Reviewed By: samparker Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62667 llvm-svn: 362953
* [PowerPC] Add R_PPC_IRELATIVEFangrui Song2019-06-061-0/+1
| | | | | | This will be used by lld's powerpc port. llvm-svn: 362713
* [PowerPC] Add missing R_PPC_* relocation typesFangrui Song2019-05-261-0/+32
| | | | | | | | While people mostly care about 64-bit, some systems need basic lib32 support. The plan is to make lld (see PR40888) capable of linking some applications (PR40888). llvm-svn: 361711
* Add missed files from prev. commitAnton Korobeynikov2018-11-151-0/+16
| | | | llvm-svn: 346949
* Revert "[MSP430] Add MC layer"Davide Italiano2018-11-081-16/+0
| | | | | | | | | | | This commit broke the module buildbots. Error: lib/Target/MSP430/MSP430GenAsmMatcher.inc:1027:1: error: redundant namespace 'llvm' [-Wmodules-import-nested-redundant] ^ llvm-svn: 346410
* [MSP430] Add MC layerAnton Korobeynikov2018-11-081-0/+16
| | | | | | | | | | | | | | | | | Summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Reviewers: asl Reviewed By: asl Subscribers: pftbest, krisb, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D53661 llvm-svn: 346374
* [WebAssembly] Remove ELF file support.Sam Clegg2018-07-161-8/+0
| | | | | | | | | This support was partial and temporary. Now that we have wasm object file support its no longer needed. Differential Revision: https://reviews.llvm.org/D48744 llvm-svn: 337222
* [PowerPC] Add support for high and higha symbol modifiers on tls modifers.Sean Fertile2018-06-151-0/+8
| | | | | | | | | | Enables using the high and high-adjusted symbol modifiers on thread local storage modifers in powerpc assembly. Needed to be able to support 64 bit thread-pointer and dynamic-thread-pointer access sequences. Differential Revision: https://reviews.llvm.org/D47754 llvm-svn: 334856
* [PPC64] Support "symbol@high" and "symbol@higha" symbol modifers.Sean Fertile2018-06-151-0/+4
| | | | | | | | | | Add support for the "@high" and "@higha" symbol modifiers in powerpc64 assembly. The modifiers represent accessing the segment consiting of bits 16-31 of a 64-bit address/offset. Differential Revision: https://reviews.llvm.org/D47729 llvm-svn: 334855
* Add R_PPC64_IRELATIVE to PPC64 relocations.Sean Fertile2018-05-241-0/+2
| | | | | | | | Relocation is needed for use in lld, which has the accompanying test. Differential Review: https://reviews.llvm.org/D46876 llvm-svn: 333200
* Revert and accidentally committed revert commitDylan McKay2017-12-091-2/+3
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-091-3/+2
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* [AVR] Override ParseDirectiveLeslie Zhai2017-12-071-2/+3
| | | | | | | | | | Reviewers: dylanmckay, kparzysz Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D38029 llvm-svn: 320009
* Add base relative relocation record that can be used for the following case ↵Tony Tye2017-10-161-0/+1
| | | | | | | | | | | | | | (OpenCL example): static __global int Var = 0; __global int* Ptr[] = {&Var}; ... In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol. Differential Revision: https://reviews.llvm.org/D38909 llvm-svn: 315935
* [ARC] Prepare the implementation of relocation for LLDLeslie Zhai2017-09-131-0/+74
| | | | | | | | | | | | Reviewers: ruiu, kparzysz, petecoup, rafael Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37556 llvm-svn: 313109
* [RISCV] Recognize new relocation typesAlex Bradbury2017-08-151-0/+9
| | | | | | | | | | | This patch adds all RISC-V relocation types, as of binutils 2.29. Note that R_RISCV32_PCREL is not currently documented in the RISC-V ELF PSABI. Differential Revision: https://reviews.llvm.org/D36455 Patch by Chih-Mao Chen (@PkmX) llvm-svn: 310914
* Move Object format code to lib/BinaryFormat.Zachary Turner2017-06-0716-0/+1276
This creates a new library called BinaryFormat that has all of the headers from llvm/Support containing structure and layout definitions for various types of binary formats like dwarf, coff, elf, etc as well as the code for identifying a file from its magic. Differential Revision: https://reviews.llvm.org/D33843 llvm-svn: 304864
OpenPOWER on IntegriCloud