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* [lldb] Fix offset intersection bug between MPX and AVX registersGuilherme Andrade2019-10-311-0/+2
| | | | | | | | | | | | | | | | | Summary: This change increases the offset of MPX registers (by 128) so they do not overlap with the offset associated with AVX registers. That was causing MPX data in GDBRemoteRegisterContext::m_reg_data to get overwritten. Reviewers: labath Reviewed By: labath Subscribers: JDevlieghere, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D68874
* [Linux/x86] Fix writing of non-gpr registers on newer processorsPavel Labath2019-04-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We're using ptrace(PTRACE_SETREGSET, NT_X86_XSTATE) to write all non-gpt registers on x86 linux. Unfortunately, this method has a quirk, where the kernel rejects all attempts to write to this area if one supplies a buffer which is smaller than the area size (even though the kernel will happily accept partial reads from it). This means that if the CPU supports some new registers/extensions that we don't know about (in my case it was the PKRU extension), we will fail to write *any* non-gpr registers, even those that we know about. Since this is a situation that's likely to appear again and again, I add code to NativeRegisterContextLinux_x86_64 to detect the runtime size of the area, and allocate an appropriate buffer. This does not mean that we will start automatically supporting all new extensions, but it does mean that the new extensions will not prevent the old ones from working. This fixes tests attempting to write to non-gpr registers on new intel processors (cca Kaby Lake Refresh). Reviewers: jankratochvil, davezarzycki Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D59991 llvm-svn: 357376
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Kill struct IOVECPavel Labath2017-12-011-1/+2
| | | | | | | | | | | struct iovec is used as an interface to system (posix) api's. As such, we shouldn't be using it in os-independent code, and we shouldn't be defining our own iovec replacements. Fortunately, its usage was not very widespread, so the removal was very easy -- I simply moved a couple declarations into os-specific code. llvm-svn: 319536
* Fix floating point register write on new x86 linux kernelsPavel Labath2017-11-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: New linux kernels (on systems that support the XSAVES instruction) will not update the inferior registers unless the corresponding flag in the XSAVE header is set. Normally this flag will be set in our image of the XSAVE area (since we obtained it from the kernel), but if the inferior has never used the corresponding register set, the respective flag can be clear. This fixes the issue by making sure we explicitly set the flags corresponding to the registers we modify. I don't try to precisely match the flags to set on each write, as the rules could get quite complicated -- I use a simpler over-approximation instead. This was already caught by test_fp_register_write, but that was only because the code that ran before main() did not use some of the register sets. Since nothing in this test relies on being stopped in main(), I modify the test to stop at the entry point instead, so we can be sure the inferior did not have a chance to access these registers. Reviewers: clayborg, valentinagiusti Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D40434 llvm-svn: 319161
* Clean up NativeRegisterContextPavel Labath2017-11-101-2/+1
| | | | | | | | | | | | | | | | | | | | | Summary: This commit removes the concrete_frame_idx member from NativeRegisterContext and related functions, which was always set to zero and never used. I also change the native thread class to store a NativeRegisterContext as a unique_ptr (documenting the ownership) and make sure it is always initialized (most of the code was already blindly dereferencing the register context pointer, assuming it would always be present -- this makes its treatment consistent). Reviewers: eugene, clayborg, krytarowski Subscribers: aemerson, sdardis, nemanjai, javed.absar, arichardson, kristof.beyls, kbarton, uweigand, alexandreyy, lldb-commits Differential Revision: https://reviews.llvm.org/D39837 llvm-svn: 317881
* Rename Error -> Status.Zachary Turner2017-05-121-15/+16
| | | | | | | | | | | | | | | This renames the LLDB error class to Status, as discussed on the lldb-dev mailing list. A change of this magnitude cannot easily be done without find and replace, but that has potential to catch unwanted occurrences of common strings such as "Error". Every effort was made to find all the obvious things such as the word "Error" appearing in a string, etc, but it's possible there are still some lingering occurences left around. Hopefully nothing too serious. llvm-svn: 302872
* Refactor NativeRegisterContextLinux_x86_64 code.Valentina Giusti2016-09-211-6/+0
| | | | | | | | | | | | This patch refactors the way the XState type is checked and, in order to simplify the code, it removes the usage of the 'cpuid' instruction: just checking if the ptrace calls done throuhg ReadFPR is enough to verify both if there is HW support and if there is kernel support. Also the XCR0 bits are enough to check if there is both HW and kernel support for AVX and MPX. Differential Revision: https://reviews.llvm.org/D24764 llvm-svn: 282072
* Use 'enum class' instead of 'enum' in NativeRegisterContextLinux_x86_x64.Valentina Giusti2016-09-141-2/+2
| | | | | | | | | | Reviewers: labath, clayborg, zturner Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D24578 llvm-svn: 281528
* Use Intel CPU flags to determine target supported features.Valentina Giusti2016-09-141-6/+11
| | | | | | | | | | | | | Summary: This patch uses the instruction CPUID to verify that FXSAVE, XSAVE, AVX and MPX are supported by the target hardware. In case the HW supports XSAVE, and at least one of the extended register sets, it further checks if the target software has the kernel support for such features, by verifying that their XSAVE part is correctly managed. Differential Revision: https://reviews.llvm.org/D24559 llvm-svn: 281507
* Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.Valentina Giusti2016-09-081-3/+12
| | | | | | | | | | | | Summary: Signed-off-by: Valentina Giusti <valentina.giusti@intel.com> Reviewers: dvlahovski, granata.enrico, clayborg, labath Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D24255 llvm-svn: 280942
* *** This commit represents a complete reformatting of the LLDB source codeKate Stone2016-09-061-107/+74
| | | | | | | | | | | | | | | | | | | | | | | *** to conform to clang-format’s LLVM style. This kind of mass change has *** two obvious implications: Firstly, merging this particular commit into a downstream fork may be a huge effort. Alternatively, it may be worth merging all changes up to this commit, performing the same reformatting operation locally, and then discarding the merge for this particular commit. The commands used to accomplish this reformatting were as follows (with current working directory as the root of the repository): find . \( -iname "*.c" -or -iname "*.cpp" -or -iname "*.h" -or -iname "*.mm" \) -exec clang-format -i {} + find . -iname "*.py" -exec autopep8 --in-place --aggressive --aggressive {} + ; The version of clang-format used was 3.9.0, and autopep8 was 1.2.4. Secondly, “blame” style tools will generally point to this commit instead of a meaningful prior commit. There are alternatives available that will attempt to look through this change and find the appropriate prior commit. YMMV. llvm-svn: 280751
* Revert "Intel(R) Memory Protection Extensions (Intel(R) MPX) support."Dimitar Vlahovski2016-09-061-16/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit rL280668 because the register tests fail on i386 Linux. I investigated a little bit what causes the failure - there are missing registers when running 'register read -a'. This is the output I got at the bottom: """ ... Memory Protection Extensions: bnd0 = {0x0000000000000000 0x0000000000000000} bnd1 = {0x0000000000000000 0x0000000000000000} bnd2 = {0x0000000000000000 0x0000000000000000} bnd3 = {0x0000000000000000 0x0000000000000000} unknown: 2 registers were unavailable. """ Also looking at the packets exchanged between the client and server: """ ... history[308] tid=0x7338 < 19> send packet: $qRegisterInfo4a#d7 history[309] tid=0x7338 < 130> read packet: $name:bnd0;bitsize:128;offset:1032;encoding:vector;format:vector-uint64;set:Memory Protection Extensions;ehframe:101;dwarf:101;#48 history[310] tid=0x7338 < 19> send packet: $qRegisterInfo4b#d8 history[311] tid=0x7338 < 130> read packet: $name:bnd1;bitsize:128;offset:1048;encoding:vector;format:vector-uint64;set:Memory Protection Extensions;ehframe:102;dwarf:102;#52 history[312] tid=0x7338 < 19> send packet: $qRegisterInfo4c#d9 history[313] tid=0x7338 < 130> read packet: $name:bnd2;bitsize:128;offset:1064;encoding:vector;format:vector-uint64;set:Memory Protection Extensions;ehframe:103;dwarf:103;#53 history[314] tid=0x7338 < 19> send packet: $qRegisterInfo4d#da history[315] tid=0x7338 < 130> read packet: $name:bnd3;bitsize:128;offset:1080;encoding:vector;format:vector-uint64;set:Memory Protection Extensions;ehframe:104;dwarf:104;#54 history[316] tid=0x7338 < 19> send packet: $qRegisterInfo4e#db history[317] tid=0x7338 < 76> read packet: $name:bndcfgu;bitsize:64;offset:1096;encoding:vector;format:vector-uint8;#99 history[318] tid=0x7338 < 19> send packet: $qRegisterInfo4f#dc history[319] tid=0x7338 < 78> read packet: $name:bndstatus;bitsize:64;offset:1104;encoding:vector;format:vector-uint8;#8e ... """ The bndcfgu and bndstatus registers don't have the 'Memory Protections Extension' set. I looked at the code and it seems that that is set correctly. So I'm not sure what's the problem or where does it come from. Also there is a second failure related to something like this in the tests: """ registerSet.GetName().lower() """ For some reason the registerSet.GetName() returns None. llvm-svn: 280703
* Intel(R) Memory Protection Extensions (Intel(R) MPX) support.Valentina Giusti2016-09-051-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The Intel(R) Memory Protection Extensions (Intel(R) MPX) associates pointers to bounds, against which the software can check memory references to prevent out of bound memory access. This patch allows accessing the MPX registers: * bnd0-3: 128-bit registers to hold the bound values, * bndcfgu, bndstatus: 64-bit configuration registers, This patch also adds read/write tests for the MPX registers in the register command tests and adds a new subdirectory for MPX specific tests. Signed-off-by: Valentina Giusti <valentina.giusti@intel.com> Reviewers: labath, granata.enrico, lldb-commits, clayborg Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D24187 llvm-svn: 280668
* Bug 24457 - X87 FPU Special Purpose RegistersAbhishek Aggarwal2015-09-071-0/+1
| | | | | | | | | | | | | | | | | | | | Summary: - For 'register read --all' command on x86_64-Linux Platform: -- Provide correct values of X87 FPU Special Purpose Registers -- Both 32-bit & 64-bit inferiors give correct values on this Platform - Added a Test Vector: -- To verify the expected behaviour of the command Signed-off-by: Abhishek Aggarwal <abhishek.a.aggarwal@intel.com> Reviewers: ashok.thirumurthi, granata.enrico, tfiala, clayborg Differential Revision: http://reviews.llvm.org/D12592 llvm-svn: 246955
* Move register reading form NativeProcessLinux to NativeRegisterContextLinux*Tamas Berghammer2015-05-261-24/+24
| | | | | | | | | | | | | | | | | This change reorganize the register read/write code inside lldb-server on Linux with moving the architecture independent code into a new class called NativeRegisterContextLinux and all of the architecture dependent code into the appropriate NativeRegisterContextLinux_* class. As part of it the compilation of the architecture specific register contexts are only compiled on the specific architecture because they can't be used in other cases. The purpose of this change is to remove a lot of duplicated code from the different register contexts and to remove the architecture dependent codes from the global NativeProcessLinux class. Differential revision: http://reviews.llvm.org/D9935 llvm-svn: 238196
* This patch adds support for setting/clearing hardware watchpoints and ↵Omair Javaid2015-05-151-1/+1
| | | | | | | | breakpoints on AArch64 (Arm v8) 64-bit hardware. http://reviews.llvm.org/D9706 llvm-svn: 237419
* Move several plugin to its own namespaceTamas Berghammer2015-03-311-5/+8
| | | | | | | | | | | | | Affected paths: * Plugins/Platform/Android/* * Plugins/Platform/Linux/* * Plugins/Platform/gdb-server/* * Plugins/Process/Linux/* * Plugins/Process/gdb-remote/* Differential revision: http://reviews.llvm.org/D8654 llvm-svn: 233679
* Report watchpoint hits during single stepping.Chaoren Lin2015-03-191-2/+5
| | | | | | | | | | | | | | | | | | Summary: Reorganized NativeProcessLinux::MonitorSIGTRAP to check for watchpoint hits on TRAP_TRACE. Added test for stepping over watchpoints. https://llvm.org/bugs/show_bug.cgi?id=22814 Reviewers: ovyalov, tberghammer, vharron, clayborg Subscribers: jingham, labath, lldb-commits Differential Revision: http://reviews.llvm.org/D8404 llvm-svn: 232784
* Report stopped by trace if none of the watchpoint was hitTamas Berghammer2015-03-171-3/+3
| | | | | | | | | | Some linux kernel reports a watchpoint hit after single stepping even when no watchpoint was hit. This CL looks for a watchpoint which was hit and reports a stop by trace if it haven't found any. Differential revision: http://reviews.llvm.org/D8081 llvm-svn: 232482
* Report the actual user register count from NativeRegisterContextLinux_x86_64Tamas Berghammer2015-03-091-0/+3
| | | | | | | | | Thic change have effect wehn the AVX registers aren't available with reporting the count of user registers without them. Differential revision: http://reviews.llvm.org/D8111 llvm-svn: 231638
* Fix four missing 'override' specifiers found with the ClangChandler Carruth2015-02-131-4/+4
| | | | | | | | '-Winconsistent-missing-override' warning. I suggest folks use this to ensure that override is consistently used to mark virtual function overrides. llvm-svn: 229084
* Implement setting and clearing watchpoints.Chaoren Lin2015-02-031-0/+26
| | | | llvm-svn: 227930
* Moving header files from source/Host/common to proper location.Chaoren Lin2015-02-031-1/+1
| | | | llvm-svn: 227929
* Enable llgs to build against experimental Android AOSP ↵Todd Fiala2014-09-271-2/+2
| | | | | | | | | | | | lldb/llvm/clang/compiler-rt repos. See http://reviews.llvm.org/D5495 for more details. These are changes that are part of an effort to support building llgs, within the AOSP source tree, using the Android.mk build system, when using the llvm/clang/lldb git repos from AOSP replaced with the experimental ones currently in github.com/tfiala/aosp-{llvm,clang,lldb,compiler-rt}. llvm-svn: 218568
* Fixup Windows build breaks for the llgs upstream.Todd Fiala2014-06-301-0/+135
Also moves NativeRegisterContextLinux* files into the Linux directory. These, like NativeProcessLinux, should only be built on Linux or a cross compiler with proper headers. llvm-svn: 212074
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