summaryrefslogtreecommitdiffstats
path: root/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [LLDB] [ARM] Use r11 as frame pointer on Windows on ARMMartin Storsjö2019-11-291-2/+6
| | | | | | | Extend EmulateMOVRdRm to identify "mov r11, sp" in thumb mode as setting the frame pointer, if r11 is the frame pointer register. Differential Revision: https://reviews.llvm.org/D70797
* Support Linux signal return trampolines in frame initializationJoseph Tremoulet2019-07-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add __kernel_rt_sigreturn to the list of trap handlers for Linux (it's used as such on aarch64 at least), and __restore_rt as well (used on x86_64). Skip decrement-and-recompute for trap handlers in InitializeNonZerothFrame, as signal dispatch may point the child frame's return address to the start of the return trampoline. Parse the 'S' flag for signal handlers from eh_frame augmentation, and propagate it to the unwind plan. Reviewers: labath, jankratochvil, compnerd, jfb, jasonmolenda Reviewed By: jasonmolenda Subscribers: clayborg, MaskRay, wuzish, nemanjai, kbarton, jrtc27, atanasyan, jsji, javed.absar, kristof.beyls, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D63667 llvm-svn: 366580
* [lldb] NFC modernize codebase with modernize-use-nullptrKonrad Kleine2019-05-231-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: NFC = [[ https://llvm.org/docs/Lexicon.html#nfc | Non functional change ]] This commit is the result of modernizing the LLDB codebase by using `nullptr` instread of `0` or `NULL`. See https://clang.llvm.org/extra/clang-tidy/checks/modernize-use-nullptr.html for more information. This is the command I ran and I to fix and format the code base: ``` run-clang-tidy.py \ -header-filter='.*' \ -checks='-*,modernize-use-nullptr' \ -fix ~/dev/llvm-project/lldb/.* \ -format \ -style LLVM \ -p ~/llvm-builds/debug-ninja-gcc ``` NOTE: There were also changes to `llvm/utils/unittest` but I did not include them because I felt that maybe this library shall be updated in isolation somehow. NOTE: I know this is a rather large commit but it is a nobrainer in most parts. Reviewers: martong, espindola, shafik, #lldb, JDevlieghere Reviewed By: JDevlieghere Subscribers: arsenm, jvesely, nhaehnle, hiraditya, JDevlieghere, teemperor, rnkovacs, emaste, kubamracek, nemanjai, ki.stfu, javed.absar, arichardson, kbarton, jrtc27, MaskRay, atanasyan, dexonsmith, arphaman, jfb, jsji, jdoerfert, lldb-commits, llvm-commits Tags: #lldb, #llvm Differential Revision: https://reviews.llvm.org/D61847 llvm-svn: 361484
* Fix UNPREDICTABLE check in EmulateInstructionARM::EmulateADDRegShiftRaphael Isemann2019-04-271-1/+1
| | | | | | | | | | | | | | | | | | | Summary: As reported in LLVM bug 41487, the check in this function is wrong and should be the same as the described check in the comment (which is correctly copied from the ARM ISA reference). Reviewers: #lldb, davide, JDevlieghere Reviewed By: #lldb, davide, JDevlieghere Subscribers: davide, javed.absar, kristof.beyls, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D60654 llvm-svn: 359387
* [NFC] Remove ASCII lines from commentsJonas Devlieghere2019-04-101-40/+0
| | | | | | | | | | | | | | | | | | | | | | | A lot of comments in LLDB are surrounded by an ASCII line to delimit the begging and end of the comment. Its use is not really consistent across the code base, sometimes the lines are longer, sometimes they are shorter and sometimes they are omitted. Furthermore, it looks kind of weird with the 80 column limit, where the comment actually extends past the line, but not by much. Furthermore, when /// is used for Doxygen comments, it looks particularly odd. And when // is used, it incorrectly gives the impression that it's actually a Doxygen comment. I assume these lines were added to improve distinguishing between comments and code. However, given that todays editors and IDEs do a great job at highlighting comments, I think it's worth to drop this for the sake of consistency. The alternative is fixing all the inconsistencies, which would create a lot more churn. Differential revision: https://reviews.llvm.org/D60508 llvm-svn: 358135
* Replace 'ap' with 'up' suffix in variable names. (NFC)Jonas Devlieghere2019-02-131-6/+6
| | | | | | | | | | | | | | | | | The `ap` suffix is a remnant of lldb's former use of auto pointers, before they got deprecated. Although all their uses were replaced by unique pointers, some variables still carried the suffix. In r353795 I removed another auto_ptr remnant, namely redundant calls to ::get for unique_pointers. Jim justly noted that this is a good opportunity to clean up the variable names as well. I went over all the changes to ensure my find-and-replace didn't have any undesired side-effects. I hope I didn't miss any, but if you end up at this commit doing a git blame on a weirdly named variable, please know that the change was unintentional. llvm-svn: 353912
* Remove redundant ::get() for smart pointer. (NFC)Jonas Devlieghere2019-02-121-2/+2
| | | | | | | | This commit removes redundant calls to smart pointer’s ::get() method. https://clang.llvm.org/extra/clang-tidy/checks/readability-redundant-smartptr-get.html llvm-svn: 353795
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Simplify Boolean expressionsJonas Devlieghere2018-12-151-67/+25
| | | | | | | | | | | This patch simplifies boolean expressions acorss LLDB. It was generated using clang-tidy with the following command: run-clang-tidy.py -checks='-*,readability-simplify-boolean-expr' -format -fix $PWD Differential revision: https://reviews.llvm.org/D55584 llvm-svn: 349215
* Remove comments after header includes.Jonas Devlieghere2018-11-111-2/+1
| | | | | | | | | | This patch removes the comments following the header includes. They were added after running IWYU over the LLDB codebase. However they add little value, are often outdates and burdensome to maintain. Differential revision: https://reviews.llvm.org/D54385 llvm-svn: 346625
* Upstreaming the BridgeOS device support and the Jason Molenda2018-10-111-0/+1
| | | | | | | | | | | | | | | LC_BUILD_VERSION load command handling - this commit is a combination of patches by Adrian Prantl and myself. llvm::Triple::BridgeOS isn't defined yet, so all references to that are currently commented out. Also update Xcode project file to build the NativePDB etc plugins. <rdar://problem/43353615> llvm-svn: 344209
* Change AddressClass type from 'enum' to 'enum class'.Tatyana Krasnukha2018-06-261-3/+3
| | | | | | If we have a function with signature f(addr_t, AddressClass), it is easy to muddle up the order of arguments without any warnings from compiler. 'enum class' prevents passing integer in place of AddressClass and vice versa. llvm-svn: 335599
* Reflow paragraphs in comments.Adrian Prantl2018-04-301-311/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is intended as a clean up after the big clang-format commit (r280751), which unfortunately resulted in many of the comment paragraphs in LLDB being very hard to read. FYI, the script I used was: import textwrap import commands import os import sys import re tmp = "%s.tmp"%sys.argv[1] out = open(tmp, "w+") with open(sys.argv[1], "r") as f: header = "" text = "" comment = re.compile(r'^( *//) ([^ ].*)$') special = re.compile(r'^((([A-Z]+[: ])|([0-9]+ )).*)|(.*;)$') for line in f: match = comment.match(line) if match and not special.match(match.group(2)): # skip intentionally short comments. if not text and len(match.group(2)) < 40: out.write(line) continue if text: text += " " + match.group(2) else: header = match.group(1) text = match.group(2) continue if text: filled = textwrap.wrap(text, width=(78-len(header)), break_long_words=False) for l in filled: out.write(header+" "+l+'\n') text = "" out.write(line) os.rename(tmp, sys.argv[1]) Differential Revision: https://reviews.llvm.org/D46144 llvm-svn: 331197
* Move ArchSpec to the Utility modulePavel Labath2017-11-131-1/+1
| | | | | | | | | | | | | The rationale here is that ArchSpec is used throughout the codebase, including in places which should not depend on the rest of the code in the Core module. This commit touches many files, but most of it is just renaming of #include lines. In a couple of cases, I removed the #include ArchSpec line altogether, as the file was not using it. In one or two places, this necessitated adding other #includes like lldb-private-defines.h. llvm-svn: 318048
* Fix various warnings. NFCZachary Turner2017-03-021-352/+0
| | | | llvm-svn: 296717
* Move classes from Core -> Utility.Zachary Turner2017-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This moves the following classes from Core -> Utility. ConstString Error RegularExpression Stream StreamString The goal here is to get lldbUtility into a state where it has no dependendencies except on itself and LLVM, so it can be the starting point at which to start untangling LLDB's dependencies. These are all low level and very widely used classes, and previously lldbUtility had dependencies up to lldbCore in order to use these classes. So moving then down to lldbUtility makes sense from both the short term and long term perspective in solving this problem. Differential Revision: https://reviews.llvm.org/D29427 llvm-svn: 293941
* Break some dependencies in lldbUtility.Zachary Turner2017-02-011-0/+909
| | | | | | Differential Revision: https://reviews.llvm.org/D29359 llvm-svn: 293806
* *** This commit represents a complete reformatting of the LLDB source codeKate Stone2016-09-061-11225/+11532
| | | | | | | | | | | | | | | | | | | | | | | *** to conform to clang-format’s LLVM style. This kind of mass change has *** two obvious implications: Firstly, merging this particular commit into a downstream fork may be a huge effort. Alternatively, it may be worth merging all changes up to this commit, performing the same reformatting operation locally, and then discarding the merge for this particular commit. The commands used to accomplish this reformatting were as follows (with current working directory as the root of the repository): find . \( -iname "*.c" -or -iname "*.cpp" -or -iname "*.h" -or -iname "*.mm" \) -exec clang-format -i {} + find . -iname "*.py" -exec autopep8 --in-place --aggressive --aggressive {} + ; The version of clang-format used was 3.9.0, and autopep8 was 1.2.4. Secondly, “blame” style tools will generally point to this commit instead of a meaningful prior commit. There are alternatives available that will attempt to look through this change and find the appropriate prior commit. YMMV. llvm-svn: 280751
* Delete Host/windows/win32.hZachary Turner2016-08-091-0/+1
| | | | | | | | | | | | | | | | | | | It's always hard to remember when to include this file, and when you do include it it's hard to remember what preprocessor check it needs to be behind, and then you further have to remember whether it's windows.h or win32.h which you need to include. This patch changes the name to PosixApi.h, which is more appropriately named, and makes it independent of any preprocessor setting. There's still the issue of people not knowing when to include this, because there's not a well-defined set of things it exposes other than "whatever is missing on Windows", but at least this should make it less painful to fix when problems arise. This patch depends on LLVM revision r278170. llvm-svn: 278177
* Fix ARM instruction emulation tests on big-endian systemsUlrich Weigand2016-04-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running the ARM instruction emulation test on a big-endian system would fail, since the code doesn't respect endianness properly. In EmulateInstructionARM::TestEmulation, code assumes that an instruction opcode read in from the test file is in target byte order, but it was in fact read in in host byte order. More difficult to fix, the EmulationStateARM structure models the overlapping sregs and dregs by a union in _sd_regs. This only works correctly if the host is a little-endian system. I've removed the union in favor of a simple array containing the 32 sregs, and changed any code accessing dregs to explicitly use the correct two sregs overlaying that dreg in the proper target order. Also, the EmulationStateARM::ReadPseudoMemory and WritePseudoMemory track memory as a map of uint32_t values in host byte order, and implement 64-bit memory accessing by splitting them up into two uint32_t ones. However, callers expect memory contents to be provided in the form of a byte array (in target byte order). This means the uint32_t contents need to be byte-swapped on BE systems, and when splitting up a 64-bit access into two 32-bit ones, byte order has to be respected. Differential Revision: http://reviews.llvm.org/D18984 llvm-svn: 266314
* Consolidate the knowledge of what arm cores are always executingJason Molenda2016-04-051-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode into one method in ArchSpec, replace checks for specific cores in the disassembler with calls to this. Also call this from the arm instruction emulation code. The determination of whether a given ArchSpec is thumb-only is still a bit of a hack, but at least the hack is consolidated into a single place. In my original version of this patch http://reviews.llvm.org/D13578 I was calling into llvm's feature arm feature tables to make this determination, like #include "llvm/Support/TargetRegistry.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/../../lib/Target/ARM/ARMGenRegisterInfo.inc" #include "llvm/../../lib/Target/ARM/ARMFeatures.h" [...] std::string triple (GetTriple().getTriple()); const char *cpu = ""; const char *features_str = ""; const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple.c_str(), Error); std::unique_ptr<llvm::MCSubtargetInfo> subtarget_info_up (curr_target->createMCSubtargetInfo(triple.c_str(), cpu, features_str)); if (subtarget_info_up->getFeatureBits()[llvm::ARM::FeatureNoARM]) { return true; } but those tables are post-llvm-build generated and linking against them for all of our different build system methods was a big hiccup that I haven't had time to revisit convincingly. I'll keep that reviews.llvm.org patch around to remind myself that I need to take another run at linking against the necessary tables again in llvm. <rdar://problem/23022803> llvm-svn: 265377
* Fix handling of the arm IT instruction in the unwinderTamas Berghammer2016-02-101-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | | The IT instruction can specify condition code for up to 4 consecutive instruction and it is used quite often by clang in epilogues causing an issue when trying to unwind from locations covered by the IT instruction and for locatins inmediately after the IT instruction. Changes made to fix it: * Introduce the concept of conditional instruction block what is a list of consecutive instructions with the same condition. We update the unwind information during the conditional instruction block and when we reach the end of it (first instruction with a differemt condition) then we restore the unwind information we had before the condition. * Fix a bug in the ARM instruction emulator where neither PC nor the ITSTATE was advanced when we reached an instruction what we can't decode. After the change we have no regression on android-arm running the regular test suit and TestStandardUnwind also passes when running it with clang as the compiler (previously it failed on an IT instruction). Differential revision: http://reviews.llvm.org/D16814 llvm-svn: 260368
* Fix single stepping over the IT instructionTamas Berghammer2016-02-021-5/+16
| | | | | | | | | | | | | | | | | The ARM instruction emulator had 2 bugs related to the handling of the IT instruction causing an error in single stepping: * We haven't initialized the IT mask from the CPSR so if the last instruction of the IT block is a branch and the condition is false then the emulator evaluated the branch what resulted in an incorrect pc for the next instruction. * The ITSTATE was advanced before the execution of each instruction. As a result the emulator was using the condition of following instruction in every case. The ITSTATE should be edvanced after the execution of an instruction except after an IT instruction. Differential revision: http://reviews.llvm.org/D16772 llvm-svn: 259509
* Fix emulation of the thumb str instructionTamas Berghammer2015-12-211-2/+10
| | | | llvm-svn: 256147
* Fix the emulation of arm strd instructionTamas Berghammer2015-12-181-2/+5
| | | | | | | The incorrect instruction emulation caused issues in the stack unwinding code when strd was used to push 2 register to the stack with writeback. llvm-svn: 256000
* Add support for the new (added last week) llvm::Triple::WatchOS and ::TvOSJason Molenda2015-11-051-1/+2
| | | | | | | | | | in places where we check for Triple::IOS. They're mostly the same as far as lldb is conerned. . Also add a base cass implementation for Process::IsAlive - Greg added this last year but it didn't get upstreamed. llvm-svn: 252227
* Make use of lldv::Triple::isAndroidTamas Berghammer2015-10-141-1/+1
| | | | | | | | It is a new function added to the llvm::Triple class to simplify the checking if we are targeting android to clean up the confusion between android being an OS or an environment. llvm-svn: 250286
* Fix assertion failure caused by r245546Tamas Berghammer2015-08-211-2/+1
| | | | | | | | Change the way EmulateInstruction::eContextPopRegisterOffStack handled in UnwindAssemblyInstEmulation::WriteRegister to accomodate for additional cases when eContextPopRegisterOffStack (pop PC/FLAGS). llvm-svn: 245690
* Improve instruction emulation based stack unwindingTamas Berghammer2015-08-201-4/+7
| | | | | | | | | | | On ARM there is no difference petween a pop and a load instruction so a register can be loaded multiple times during the function. Add check to threat the load as a restore only if it do the restore from the same location where the register was saved. Differential revision: http://reviews.llvm.org/D11947 llvm-svn: 245546
* Fix read/write context in EmulateInstructionARM strd/ldrdTamas Berghammer2015-07-291-4/+17
| | | | llvm-svn: 243521
* Remove non-utf-8 characters from EmulateInstructionARMTamas Berghammer2015-07-291-142/+142
| | | | llvm-svn: 243520
* Improve conditional opcode handling in emulation based unwindingTamas Berghammer2015-07-171-45/+22
| | | | | | | | | | Don't chane the CFI information when a conditional instruction is emulated (eg.: popeq {r0, pc}) because the CFI for the next instruction should be the same as the CFI for the current instruction. Differential revision: http://reviews.llvm.org/D11258 llvm-svn: 242519
* Improve instruction emulation based stack unwinding on ARMTamas Berghammer2015-06-241-111/+203
| | | | | | | | | | | | | | | | | | | | | | | * Add and fix the emulation of several instruction. * Disable frame pointer usage on Android. * Specify return address register for the unwind plan instead of explict tracking the value of RA. * Replace prologue detection heuristics (unreliable in several cases) with a logic to follow the branch instructions and restore the CFI value based on them. The target address for a branch should have the same CFI as the source address (if they are in the same function). * Handle symbols in ELF files where the symbol size is not specified with calcualting their size based on the next symbol (already done in MachO files). * Fix architecture in FuncUnwinders with filling up the inforamtion missing from the object file with the architecture of the target. * Add code to read register wehn the value is set to "IsSame" as it meanse the value of a register in the parent frame is the same as the value in the current frame. Differential revision: http://reviews.llvm.org/D10447 llvm-svn: 240533
* Fix write register context in EmulateInstructionARM::EmulateMOVRdRmTamas Berghammer2015-05-281-1/+4
| | | | llvm-svn: 238431
* Fix write register context in EmulateInstructionARM::EmulateADDRdSPImmTamas Berghammer2015-05-281-2/+5
| | | | llvm-svn: 238410
* Fix write register context in EmulateInstructionARM::EmulateMOVRdRmTamas Berghammer2015-05-271-3/+3
| | | | llvm-svn: 238312
* Fix encoding of BX instrucion in EmulateInstructionARMTamas Berghammer2015-05-181-1/+1
| | | | llvm-svn: 237570
* Fix arm instruction emulation of add (imm) and sub (imm)Tamas Berghammer2015-05-131-35/+48
| | | | | | Differential revision: http://reviews.llvm.org/D9704 llvm-svn: 237240
* Fix thumb condition extraction in ARM instrcution emulatorTamas Berghammer2015-05-111-2/+2
| | | | llvm-svn: 236988
* Fix condition detection in EmulateInstructionARMTamas Berghammer2015-04-241-2/+1
| | | | | | | | | | | | | The condition detection code is calculating the result of the condition based on the first 3 bit of the condition and then negate it if the LSB of the condition is set. It works for the normal conditions but 0b1110 and 0b1111 are special as both of them should evaluate to true independently the value of CPSR. This CL removes the negating logic from those cases. Differential revision: http://reviews.llvm.org/D9219 llvm-svn: 235715
* Fix order of b and blx instrction in EmulateInstructionARMTamas Berghammer2015-04-241-2/+2
| | | | | | | | | | In the previous ordering some "blx <label>" instruction was recognised as "b #imm24" instructions causing a failure in the instruction emulator. Differential revision: http://reviews.llvm.org/D9218 llvm-svn: 235714
* Fix write register context for arm "add<c> <Rd>, sp, #imm"Tamas Berghammer2015-04-241-1/+5
| | | | | | Differential revision: http://reviews.llvm.org/D9213 llvm-svn: 235713
* Update cpsr register in BLX instruction emulationTamas Berghammer2015-04-231-0/+7
| | | | | | | | | Write the new cpsr value into the cpsr register if the BL or the BLX instruction change the instruction set on arm. Differential revision: http://reviews.llvm.org/D9188 llvm-svn: 235585
* UnwindPlan::Row refactor -- add support for CFA set by a DWARF expressionPavel Labath2015-02-231-1/+1
| | | | | | | | | | | | | | | | | | | Summary: This change refactors UnwindPlan::Row to be able to store the fact that the CFA is value is set by evaluating a dwarf expression (DW_CFA_def_cfa_expression). This is achieved by creating a new class CFAValue and moving all CFA setting/getting code there. Note that code using the new CFAValue::isDWARFExpression is not yet present and will be added in a follow-up patch. Therefore, this patch should not change the functionality in any way. Test Plan: Ran tests on Mac and Linux. No regressions detected. Reviewers: jasonmolenda, clayborg Subscribers: lldb-commits Differential Revision: http://reviews.llvm.org/D7755 llvm-svn: 230210
* Add #if 0 around unreachable block of code to suppress warnings.Jason Molenda2014-10-171-0/+2
| | | | | | clang warnings. llvm-svn: 220025
* Replace uint32_t by lldb::RegisterKing in register context API.Jean-Daniel Dupas2014-07-021-3/+5
| | | | llvm-svn: 212172
* lldb: remove adhoc implementation of array_sizeofSaleem Abdulrasool2014-06-271-2/+3
| | | | | | | | Replace adhoc inline implementation of llvm::array_lengthof in favour of the implementation in LLVM. This is simply a cleanup change, no functional change intended. llvm-svn: 211868
* Fix a few typos.Bruce Mitchener2014-06-271-9/+9
| | | | llvm-svn: 211851
* Update the checks in EmulateInstructionARM::GetFramePointerRegisterNumber Jason Molenda2014-01-061-12/+40
| | | | | | | | | | and EmulateInstructionARM::GetFramePointerDWARFRegisterNumber to recognize the Apple arm convention (of using r7 for the frame pointer, regardless of thumb or arm) even if the OS does not match Darwin/MacOSX/iOS. Also corrects the behavior for thumb code on non-Apple platforms. <rdar://problem/14661537> llvm-svn: 198648
* Handle endianness in the Opcode classEd Maste2013-12-091-6/+6
| | | | | | | | | Previously, an opcode set via SetOpcode32 (for example) was later extracted via GetData() as a byte sequence in host order rather than target order. Review: http://llvm-reviews.chandlerc.com/D1838 llvm-svn: 196808
OpenPOWER on IntegriCloud