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path: root/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
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* Ran the static analyzer on the codebase and found a few things.Greg Clayton2012-07-171-4/+20
* Switch nearly all of the use of the UnwindPlan::Row's to go throughJason Molenda2012-07-141-3/+3
* <rdar://problem/11358639>Greg Clayton2012-05-081-8/+26
* Make sure EmulateInstructionARM doesn't have to have "armv4", "armv6", "armv7...Greg Clayton2012-04-181-4/+4
* Add armv7s to recognized cpu type for arm instruction emulation.Jason Molenda2012-04-181-8/+10
* rdar://problem/11031743Johnny Chen2012-03-131-1/+1
* Fixed some warnings after enabling some stricter warnings in the Xcode projectGreg Clayton2011-10-311-2/+2
* Fix two logic errors uncovered by the static analyzer.Johnny Chen2011-08-161-3/+3
* Fix a logic error (Division by zero) uncovered by the static analyzer.Johnny Chen2011-08-121-1/+1
* Fix some warnings from static analyzer.Johnny Chen2011-08-121-5/+5
* Fixed some issues with ARM backtraces by not processing any push/pop Greg Clayton2011-07-061-37/+72
* Bail out if we have an invalid thumb instruction.Johnny Chen2011-06-021-2/+4
* Turn the commented-out assert()'s into appropriate bail-out actions.Johnny Chen2011-06-021-2/+5
* When emulating an ill-formed instruction, we should bail out instead of asser...Johnny Chen2011-06-021-35/+100
* Remove asserts that will crash LLDB. These should be changed to returnGreg Clayton2011-06-021-14/+14
* EmulateShiftReg() also accepts shifter type of SRType_ROR.Johnny Chen2011-06-021-1/+4
* Fixed an issue in the EmulateInstructionARM there the IT opcode was trying toGreg Clayton2011-05-231-5/+41
* Added a way to resolve an load address from a target:Greg Clayton2011-05-181-1/+4
* Moved all code from ArchDefaultUnwindPlan and ArchVolatileRegs into theirGreg Clayton2011-05-111-4/+3
* While implementing unwind information using UnwindAssemblyInstEmulation I ranGreg Clayton2011-05-091-153/+151
* Added the start of the CFI row production using theGreg Clayton2011-04-291-1/+1
* Added a new OptionValue subclass for lldb::Format: OptionValueFormat. AddedGreg Clayton2011-04-271-2/+2
* Got the EmulateInstruction CFI code a lot closer to producing CFI data.Greg Clayton2011-04-261-288/+332
* Modify EmulateInstructionARM::SetArchitecture() to treat "arm" and "thumb" as...Johnny Chen2011-04-261-0/+2
* Changed the emulate instruction function to take emulate options whichGreg Clayton2011-04-261-143/+128
* Change code for reading emulation data files to read the new fileCaroline Tice2011-04-221-46/+36
* Add the infrastructure to test instruction emulations automatically.Caroline Tice2011-04-191-10/+115
* Fix bug where source & target registers were swapped in anCaroline Tice2011-04-131-2/+2
* Fix various minor bugs in the ARM instruction emulation code.Caroline Tice2011-04-131-2/+11
* Implement ARM emulation function to handle "SUBS PC, LR and related instructi...Caroline Tice2011-04-111-43/+243
* Fix various things in the instruction emulation code:Caroline Tice2011-04-081-7/+48
* Add Emulate and DumpEmulation to Instruction class.Caroline Tice2011-04-051-1/+2
* Add the rest of the mechanisms to make ARM instruction emulation usable/possi...Caroline Tice2011-04-051-19/+202
* Fix a few typos in the previous commit.Caroline Tice2011-03-311-5/+5
* Add code to emulate VLD1 (single element to all lanes) ARM instruction.Caroline Tice2011-03-311-0/+133
* Add code to emulate VST1 (single element from one lane) ARMCaroline Tice2011-03-311-2/+162
* Add code to emulate VST1 (multiple single elements) ARMCaroline Tice2011-03-311-8/+175
* Add code to emulate VLD1 (single element to one lane) floating pointCaroline Tice2011-03-311-2/+175
* Add code to emulate VLD1 (multiple single elements) ARM instruction.Caroline Tice2011-03-311-9/+178
* Add code to emulate VSTR ARM instruction (store a floating point register).Caroline Tice2011-03-311-0/+137
* Add code to emulate the VLDR Arm instruction (load a floating poitn register).Caroline Tice2011-03-311-0/+134
* Add "Bits64" utility function.Caroline Tice2011-03-311-9/+210
* Modify ARM instruction tables to allow for specifying floating point variants.Caroline Tice2011-03-311-276/+480
* Fill in code for EmulateSTRDImm and EmulateSTRDReg, to emulate theCaroline Tice2011-03-301-24/+273
* Many improvements to the Platform base class and subclasses. The base PlatformGreg Clayton2011-03-301-1/+1
* Fill in EmulateLDRDRegister to emulate LDRD (register) instruction.Caroline Tice2011-03-301-416/+105
* Fill in EmulateLDRLImmediate to emulate the LDRD (immediate) ARM instruction.Caroline Tice2011-03-301-9/+137
* Fix typo in previous check-in.Caroline Tice2011-03-301-1/+1
* Fill in EmulateSTRImmARM to emulate the STR (immediate,ARM) instruction.Caroline Tice2011-03-301-1/+94
* Fill in EmulateSTRBImmARM to emulate the STRB (immediate, ARM) instruction.Caroline Tice2011-03-301-8/+83
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