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* [ELF][HEXAGON] Add R_HEX_16_X relocationSid Manning2018-08-221-0/+18
| | | | | | | | This relocation has only 6-bits the remaining are in the extender. Differential Revision: https://reviews.llvm.org/D50603 llvm-svn: 340413
* [PPC64] Add TLS initial exec to local exec relaxationZaara Syeda2018-08-211-1/+102
| | | | | | | | | This patch adds the target call back relaxTlsIeToLe to support TLS relaxation from initial exec to local exec model. Differential Revision: https://reviews.llvm.org/D48091 llvm-svn: 340281
* [ELF] Add support for Armv5 and Armv6 compatible ThunksPeter Smith2018-08-202-36/+43
| | | | | | | | | | | | | | | | Older Arm architectures do not support the MOVT and MOVW instructions so we must use an alternative sequence of instructions to transfer control to the destination. Assuming at least Armv5 this patch adds support for Thunks that load or add to the program counter. Note that there are no Armv5 Thumb Thunks as there is no Thumb branch instruction in Armv5 that supports Thunks. These thunks will not work for Armv4t (arm7tdmi) as this architecture cannot change state from using the LDR or ADD instruction. Differential Revision: https://reviews.llvm.org/D50077 llvm-svn: 340160
* [ELF] Add support for older Arm Architectures with smaller branch rangePeter Smith2018-08-201-3/+24
| | | | | | | | | | | | | | The Thumb BL and BLX instructions on older Arm Architectures such as v5 and v6 have a constrained encoding J1 and J2 must equal 1, later Architectures relaxed this restriction allowing J1 and J2 to be used to calculate a larger immediate. This patch adds support for the old encoding, it is used when the build attributes for the input objects only contain older architectures. Differential Revision: https://reviews.llvm.org/D50076 llvm-svn: 340159
* Remove unnecessary applyMask() application.Rui Ueyama2018-08-201-1/+1
| | | | | | applyMask(0xffffffff, x) is an identity function. llvm-svn: 340152
* [ELF][HEXAGON] Add R_HEX_32 supportSid Manning2018-08-141-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D50657 llvm-svn: 339677
* [ELF][HEXAGON] Add R_HEX_8_X relocationSid Manning2018-08-101-0/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D50577 llvm-svn: 339477
* [ELF][HEXAGON] Add R_HEX_HI16/R_HEX_LO16 relocationsSid Manning2018-08-091-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D50520 llvm-svn: 339371
* Support RISC-VRui Ueyama2018-08-091-0/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
* Add R_HEX_6_X relocation supportSid Manning2018-08-091-0/+44
| | | | | | | | | This is a larger patch. This relocation has irregular immediate masks that require a lookup to find the correct mask. Differential Revision: https://reviews.llvm.org/D50450 llvm-svn: 339332
* [LLD] Update split stack support to handle more generic prologues. Improve ↵Jordan Rupprecht2018-08-021-10/+13
| | | | | | | | | | error handling. Add test file for better code-coverage. Update tests to be more complete. Submitting patch on behalf of saugustine. Differential Revision: https://reviews.llvm.org/D49926 llvm-svn: 338750
* [ELF][ARM] Implement support for Tag_ABI_VFP_argsPeter Smith2018-07-311-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tag_ABI_VFP_args build attribute controls the procedure call standard used for floating point parameters on ARM. The values are: 0 - Base AAPCS (FP Parameters passed in Core (Integer) registers 1 - VFP AAPCS (FP Parameters passed in FP registers) 2 - Toolchain specific (Neither Base or VFP) 3 - Compatible with all (No use of floating point parameters) If the Tag_ABI_VFP_args build attribute is missing it has an implicit value of 0. We use the attribute in two ways: - Detect a clash in calling convention between Base, VFP and Toolchain. we follow ld.bfd's lead and do not error if there is a clash between an implicit Base AAPCS caused by a missing attribute. Many projects including the hard-float (VFP AAPCS) version of glibc contain assembler files that do not use floating point but do not have Tag_ABI_VFP_args. - Set the EF_ARM_ABI_FLOAT_SOFT or EF_ARM_ABI_FLOAT_HARD ELF header flag for Base or VFP AAPCS respectively. This flag is used by some ELF loaders. References: - Addenda to, and Errata in, the ABI for the ARM Architecture for Tag_ABI_VFP_args - Elf for the ARM Architecture for ELF header flags Fixes PR36009 Differential Revision: https://reviews.llvm.org/D49993 llvm-svn: 338377
* [ELF][HEXAGON] Add R_HEX_32_6_X and R_HEX_12_XSid Manning2018-07-291-0/+6
| | | | | | And add a test. llvm-svn: 338213
* [ELF][HEXAGON] Add R_HEX_B15_PCREL_X relocationSid Manning2018-07-241-0/+4
| | | | | | | | Update testcase Differential Revision: https://reviews.llvm.org/D49567 llvm-svn: 337829
* [ELF][HEXAGON] Add support for R_HEX_B15_PCRELSid Manning2018-07-191-0/+4
| | | | | | | | Add support and update the testcase. Differential Revision: https://reviews.llvm.org/D49394 llvm-svn: 337494
* Add support for R_HEX_B32_PCREL_X, R_HEX_B22_PCREL_X relocationsSid Manning2018-07-191-0/+8
| | | | | | | | A couple more basic relocations plus testcase. Differential Revision: https://reviews.llvm.org/D47791 llvm-svn: 337484
* Workaround warning bug in old versions of gcc.Sterling Augustine2018-07-181-0/+6
| | | | | | https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56480 llvm-svn: 337340
* Implement framework for linking split-stack object files, and x86_64 support.Sterling Augustine2018-07-171-0/+36
| | | | llvm-svn: 337332
* [ELF][MIPS] Add mote tests on MipsArchTree routines, fix typos in error messagesSimon Atanasyan2018-07-101-16/+17
| | | | | | | | | This fix add more test cases for routines check MIPS ELF header flags and flags from .MIPS.abiflags sections. The tests use yaml2obj for object files generation because not all combinations of flags can be produced by LLVM tools. llvm-svn: 336704
* [PPC64] Add TLS local dynamic to local exec relaxationZaara Syeda2018-07-091-0/+50
| | | | | | | | | This patch adds the target call back relaxTlsLdToLe to support TLS relaxation from local dynamic to local exec model. Differential Revision: https://reviews.llvm.org/D48293 llvm-svn: 336559
* [ELF][MIPS] Simplify `checkFlags` routine and inline `rejectMicroMips64`. NFCSimon Atanasyan2018-07-061-9/+6
| | | | llvm-svn: 336414
* [ELF][MIPS] Remove support for linking microMIPS 64-bit codeSimon Atanasyan2018-07-062-19/+10
| | | | | | | | | Remove support for linking microMIPS 64-bit code because this kind of ISA is rarely used and unsupported by LLVM. Differential revision: https://reviews.llvm.org/D48949 llvm-svn: 336413
* Remove redundnat call of makeArrayRef(). NFC.Rui Ueyama2018-07-051-1/+1
| | | | llvm-svn: 336378
* Simplify PPC64::calcEFlags().Rui Ueyama2018-07-051-40/+9
| | | | | | | | | | In this file we only have to handle the v2 ABI, so what we need to do is to just make sure that all object files have v2 or unspecified version number. Differential Revision: https://reviews.llvm.org/D48112 llvm-svn: 336372
* [PPC64] Add support for R_PPC64_GOT_DTPREL16* relocationsZaara Syeda2018-06-271-0/+12
| | | | | | | | | | | | | | The local dynamic TLS access on PPC64 ELF v2 ABI uses R_PPC64_GOT_DTPREL16* relocations when a TLS variables falls outside 2 GB of the thread storage block. This patch adds support for these relocations by adding a new RelExpr called R_TLSLD_GOT_OFF which emits a got entry for the TLS variable relative to the dynamic thread pointer using the relocation R_PPC64_DTPREL64. It then evaluates the R_PPC64_GOT_DTPREL16* relocations as the got offset for the R_PPC64_DTPREL64 got entries. Differential Revision: https://reviews.llvm.org/D48484 llvm-svn: 335732
* [PPC64] Add TLS global dynamic to local exec relaxationZaara Syeda2018-06-271-0/+37
| | | | | | | | | | | | | | | This patch adds the target call back relaxTlsGdToLe to support TLS relaxation from global dynamic to local exec model. The relaxation performs the following transformation: addis r3, r2, x@got@tlsgd@ha --> nop addi r3, r3, x@got@tlsgd@l --> addis r3, r13, x@tprel@ha bl __tls_get_addr(x@tlsgd) --> nop nop --> addi r3, r3, x@tprel@l Differential Revision: https://reviews.llvm.org/D48082 llvm-svn: 335730
* [PPC64] Thread-local storage general-dynamic to initial-exec relaxation.Sean Fertile2018-06-261-0/+53
| | | | | | | | | | | | | | | | | | Patch adds support for relaxing the general-dynamic tls sequence to initial-exec. the relaxation performs the following transformation: addis r3, r2, x@got@tlsgd@ha --> addis r3, r2, x@got@tprel@ha addi r3, r3, x@got@tlsgd@l --> ld r3, x@got@tprel@l(r3) bl __tls_get_addr(x@tlsgd) --> nop nop --> add r3, r3, r13 and instead of emitting a DTPMOD64/DTPREL64 pair for x, we emit a single R_PPC64_TPREL64. Differential Revision: https://reviews.llvm.org/D48090 llvm-svn: 335651
* [ELF][X86_64] Use R_GOTREL_FROM_END instead of R_GOTREL for R_X86_64_GOTOFF64Fangrui Song2018-06-131-1/+1
| | | | | | | | | | | | | | | | | | Summary: R_X86_64_GOTOFF64: S + A - GOT R_X86_64_GOTPC{32,64}: GOT + A - P (R_GOTONLY_PC_FROM_END) R_X86_64_GOTOFF64 should use R_GOTREL_FROM_END so that in conjunction with R_X86_64_GOTPC{32,64}, the `GOT` term is neutralized. This also matches the handling of R_386_GOTOFF (S + A - GOT). Reviewers: ruiu, espindola Subscribers: emaste, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D48095 llvm-svn: 334672
* Remove needless bitwise-AND.Rui Ueyama2018-06-131-1/+1
| | | | | | Because applyMask ignores upper bits, we don't need to mask them. llvm-svn: 334647
* Make a function non-member because it doesn't depend on any class.Rui Ueyama2018-06-131-2/+1
| | | | llvm-svn: 334646
* Apply clang-format.Rui Ueyama2018-06-131-4/+2
| | | | llvm-svn: 334645
* Add Hexagon SupportSid Manning2018-06-131-0/+84
| | | | | | Differential Revision: https://reviews.llvm.org/D47791 llvm-svn: 334637
* Use shorter names for #lo, #hi, #ha, etc. NFC.Rui Ueyama2018-06-131-15/+15
| | | | | | | | Since these functions are file-local, the new names shouldn't be ambiguous. Differential Revision: https://reviews.llvm.org/D48093 llvm-svn: 334564
* Handle R_X86_64_GOTOFF64.Rui Ueyama2018-06-121-0/+3
| | | | | | | | | | | | | | | R_X86_64_GOTOFF64 is a relocation type to set to a distance betwween a symbol and the beginning of the .got section. Previously, we always created a dynamic relocation for the relocation type even though it can be resolved at link-time. Creating a dynamic relocation for R_X86_64_GOTOFF64 caused link failure for some programs that do have a relocation of the type in a .text section, as text relocations are prohibited in most configurations. Differential Revision: https://reviews.llvm.org/D48058 llvm-svn: 334534
* [ELF][PPC64] Support R_PPC64_DTPREL64 which may be emitted in .rela.debug_addrFangrui Song2018-06-121-0/+3
| | | | llvm-svn: 334533
* [ELF] Support R_X86_64_GOTPC{32,64}Fangrui Song2018-06-121-0/+5
| | | | | | | | | | Reviewers: ruiu, grimar, espindola Subscribers: emaste, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D47098 llvm-svn: 334532
* [PPC64] Support R_PPC64_DTPREL relocations.Sean Fertile2018-06-121-7/+47
| | | | | | | | Patch adds support for most of the dynamic thread pointer based relocations for local-dynamic tls. The HIGH and HIGHA versions are missing becuase they are not supported by the llvm integrated assembler yet. llvm-svn: 334465
* AMDGPU/LLD: Handle R_AMDGPU_REL64 relocationKonstantin Zhuravlyov2018-06-111-0/+2
| | | | | | | | Requires r334443 from llvm Differential Revision: https://reviews.llvm.org/D47734 llvm-svn: 334444
* [PPC64] Add support for local-exec TLS modelZaara Syeda2018-06-081-0/+23
| | | | | | | | | | | | | | | | | | | This patch adds the relocations needed support the local-exec TLS model: R_PPC64_TPREL16 R_PPC64_TPREL16_HA R_PPC64_TPREL16_LO R_PPC64_TPREL16_HI R_PPC64_TPREL16_DS R_PPC64_TPREL16_LO_DS R_PPC64_TPREL16_HIGHER R_PPC64_TPREL16_HIGHERA R_PPC64_TPREL16_HIGHEST R_PPC64_TPREL16_HIGHESTA Differential Revision: https://reviews.llvm.org/D47598 llvm-svn: 334304
* [PPC64] Add support for initial-exec TLS modelZaara Syeda2018-06-011-0/+12
| | | | | | | | | | | | | This patch adds the relocations needed support the initial-exec TLS model: R_PPC64_GOT_TPREL16_HA R_PPC64_GOT_TPREL16_LO_DS R_PPC64_GOT_TPREL16_DS R_PPC64_GOT_TPREL16_HI R_PPC64_TLS Differential Revision: https://reviews.llvm.org/D47455 llvm-svn: 333769
* [PPC64] Support R_PPC64_GOT_TLSLD16 relocations.Sean Fertile2018-05-311-0/+10
| | | | | | | | | Add support for the R_PPC64_GOT_TLSLD16 relocations used to build the address of the tls_index struct used in local-dynamic tls. Differential Revision: https://reviews.llvm.org/D47538 llvm-svn: 333681
* Rename R_TLSGD/R_TLSLD to add _GOT_FROM_END. NFC.Sean Fertile2018-05-311-2/+2
| | | | | | | | | getRelocTargetVA for R_TLSGD and R_TLSLD RelExprs calculate an offset from the end of the got, so adjust the names to reflect this. Differential Revision: https://reviews.llvm.org/D47379 llvm-svn: 333674
* [PPC64] Support General-Dynamic tls.Sean Fertile2018-05-291-0/+14
| | | | | | | | | Adds handling of all the relocation types for general-dynamic thread local storage. Differential Revision: https://reviews.llvm.org/D47325 llvm-svn: 333420
* Fix retpoline PLT for x86-64 when used for >4GB address.Rui Ueyama2018-05-251-1/+1
| | | | | | Previously, we wrote only the least significant 32 bits. llvm-svn: 333313
* Add a comment for retpoline PLT.Rui Ueyama2018-05-251-0/+9
| | | | llvm-svn: 333312
* Fix a bug that we truncated GOTPLT entries to 32 bits.Rui Ueyama2018-05-251-1/+1
| | | | llvm-svn: 333294
* [PPC64] Set the IRelative relocation type.Sean Fertile2018-05-241-0/+1
| | | | | | | Set the IRelative relocation type and extend the related test to verify. Differential Revision: https://reviews.llvm.org/D46877 llvm-svn: 333203
* [lld] Make helpers static. NFC.Benjamin Kramer2018-05-151-1/+1
| | | | llvm-svn: 332408
* [ELF][PPC64] Fix getRelExpr for R_PPC64_REL64Zaara Syeda2018-05-141-0/+1
| | | | | | | | | The relocation R_PPC64_REL64 should return R_PC for getRelExpr since it computes S + A - P. Differential Revision: https://reviews.llvm.org/D46766 llvm-svn: 332259
* [ELF][PPC64] Fix getRelExpr for R_PPC64_REL32Zaara Syeda2018-05-141-0/+1
| | | | | | | | | The relocation R_PPC64_REL32 should return R_PC for getRelExpr since it computes S + A - P. Differential Revision: https://reviews.llvm.org/D46586 llvm-svn: 332252
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