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* Add initial support for half precision builtinsJan Vesely2018-05-1757-29/+690
* rootn: Use denormal path onlyJan Vesely2018-05-151-10/+1
* remquo: Flush denormals if not supportedJan Vesely2018-05-031-0/+2
* remquo: Port from amd builtinsJan Vesely2018-05-038-0/+307
* math: Add helper function to flush denormals if not supported.Jan Vesely2018-05-031-0/+19
* clc_sqrt: Reuse unary_decl.incJan Vesely2018-05-022-50/+3
* relational/select: Condition types for half are short/ushort, not char/ucharJan Vesely2018-04-251-2/+2
* log10: Use sw implementation from amd builtinsJan Vesely2018-04-235-19/+173
* powr: Use denormal path onlyJan Vesely2018-04-171-11/+1
* pown: Use denormal path onlyJan Vesely2018-04-171-11/+1
* pow: Use denormal path onlyJan Vesely2018-04-171-11/+1
* amdgcn/fmin: Fix typos that reduced precisionJan Vesely2018-04-171-3/+3
* exp10: Port from amd builtinsJan Vesely2018-04-175-11/+157
* hypot: Port from amd builtinsJan Vesely2018-04-105-4/+108
* select: simplify implementation and fix fp16Jan Vesely2018-04-061-18/+4
* fmod: Port from amd_builtinsJan Vesely2018-04-066-12/+196
* r600: Update datalayout after LLVM r328656Jan Vesely2018-04-054-4/+4
* amdgcn: Update datalayout after LLVM r328656Jan Vesely2018-04-054-4/+4
* remainder: Port from amd builtinsJan Vesely2018-03-196-0/+235
* nan: ImplementJan Vesely2018-03-126-0/+52
* travis: Add build using llvm-6Jan Vesely2018-03-121-0/+22
* amdgcn/fmax: fcanonicalize operandsJan Vesely2018-03-082-0/+32
* amdgcn/fmin: fcanonicalize operandsJan Vesely2018-03-082-0/+32
* amdgcn,popcount: Workaround broken llvm.ctpop intrinsic on some GCN ASICsJan Vesely2018-03-083-0/+24
* integer/gentype: Add __CLC_VECSIZE macroJan Vesely2018-03-081-0/+96
* popcount: Provide function implementation rather than intrinsic redirectJan Vesely2018-03-087-6/+21
* lgamma_r: Move code from .inc to .cl fileJan Vesely2018-03-062-475/+496
* frexp: Reuse types provided by gentype.incJan Vesely2018-03-062-78/+53
* select: Add vector implementationJan Vesely2018-03-065-1/+91
* minmag: Condition variable needs to be the same bitwidth as operandsJan Vesely2018-03-062-2/+21
* maxmag: Condition variable needs to be the same bitwidth as operandsJan Vesely2018-03-062-2/+21
* Move cl_khr_fp64 exntension enablement to gentype include listsJan Vesely2018-03-0626-87/+7
* utils: Adapt to llvm r325155Jan Vesely2018-02-231-0/+4
* amdgcn: Fix build after GDS/const AS swap in r325030Jan Vesely2018-02-2317-14/+72
* amdgcn: Fix datalayout after addition of 32bit const AS in r324747Jan Vesely2018-02-234-4/+4
* r600: Fix datalayout after clang r324101Jan Vesely2018-02-2316-4/+109
* amdgcn: Fix datalayout after clang r324101Jan Vesely2018-02-2318-5/+153
* amdgpu/half_recip: Switch implementation to native_recipJan Vesely2018-02-132-0/+7
* amdgpu/half_log2: Switch implementation to native_log2Jan Vesely2018-02-132-0/+7
* amdgpu/half_log10: Switch implementation to native_log10Jan Vesely2018-02-132-0/+7
* amdgpu/half_log: Switch implementation to native_logJan Vesely2018-02-132-0/+7
* amdgpu/half_exp2: Switch implementation to native_exp2Jan Vesely2018-02-132-0/+7
* amdgpu/half_exp10: Switch implementation to native_exp10Jan Vesely2018-02-132-0/+7
* amdgpu/half_exp: Switch implementation to native_expJan Vesely2018-02-132-0/+7
* amdgpu/half_sqrt: Switch implementation to native_sqrtJan Vesely2018-02-132-0/+7
* amdgpu/half_rsqrt: Switch implementation to native_rsqrtJan Vesely2018-02-133-0/+18
* Add vstore_half_rte implementationJan Vesely2018-02-062-1/+46
* Add vstore_half_rtp implementationJan Vesely2018-02-062-1/+12
* Add vstore_half_rtn implementationJan Vesely2018-02-062-1/+43
* Add vstore_half_rtz implementationJan Vesely2018-02-062-1/+36
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