Commit message (Collapse) | Author | Age | Files | Lines | |
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* | [AMDGPU] Fix codegen for inline assembly | Yaxun Liu | 2018-03-23 | 1 | -0/+5 |
| | | | | | | | | Need to override convertConstraint to recognise amdgpu specific register names. Differential Revision: https://reviews.llvm.org/D44533 llvm-svn: 328359 | ||||
* | [AMDGPU] Allow flexible register names in inline asm constraints | Yaxun Liu | 2017-09-28 | 1 | -2/+64 |
| | | | | | | | | | | | | | | | | | | | | | | | | Currently AMDGPU inline asm only allow v and s as register names in constraints. This patch allows the following register names in constraints: (n, m is unsigned integer, n < m) v s {vn} or {v[n]} {sn} or {s[n]} {S} , where S is a special register name {v[n:m]} {s[n:m]} Differential Revision: https://reviews.llvm.org/D37568 llvm-svn: 314452 | ||||
* | AMDGPU: Add support for 's' and 'v' asm constraints | Tom Stellard | 2015-11-19 | 1 | -0/+14 |
Summary: 's' is used to specify sgprs and 'v' is used to specify vgprs. Reviewers: arsenm, echristo Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D14307 llvm-svn: 253610 |