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* [x86] Teach the builtin argument range check to allow invalid ranges inChandler Carruth2018-06-211-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dead code. This is important for C++ templates that essentially compute the valid input in a way that is constant and will cause all the invalid cases to be dead code that is deleted. Code in the wild actually does this and GCC also accepts these kinds of patterns so it is important to support it. To make this work, we provide a non-error path to diagnose these issues, and use a default-error warning instead. This keeps the relatively strict handling but prevents nastiness like SFINAE on these errors. It also allows us to safely use the system to diagnose this only when it occurs at runtime (in emitted code). Entertainingly, this required fixing the syntax in various other ways for the x86 test because we never bothered to diagnose that the returns were invalid. Since debugging these compile failures was super confusing, I've also improved the diagnostic to actually say what the value was. Most of the checks I've made ignore this to simplify maintenance, but I've checked it in a few places to make sure the diagnsotic is working. Depends on D48462. Without that, we might actually crash some part of the compiler after bypassing the error here. Thanks to Richard, Ben Kramer, and especially Craig Topper for all the help here. Differential Revision: https://reviews.llvm.org/D48464 llvm-svn: 335309
* [ARM] Add tests for the vcvtr builtinsSjoerd Meijer2018-02-161-0/+15
| | | | | | | | | This adds Sema and Codegen tests for the vcvtr builtins (because they were missing). Differential Revision: https://reviews.llvm.org/D43372 llvm-svn: 325351
* [ARM] ACLE parallel arithmetic and DSP style multiplicationsSjoerd Meijer2017-12-071-0/+184
| | | | | | | | | | | This is a follow up of r302131, in which we forgot to add SemaChecking tests. Adding these tests revealed two problems which have been fixed: - added missing intrinsic __qdbl, - properly range checking ssat16 and usat16. Differential Revision: https://reviews.llvm.org/D40888 llvm-svn: 320019
* [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.Ranjeet Singh2016-06-171-7/+19
| | | | | | | | | | Reapplying patch in r272777 which was reverted because the llvm patch which added support for generating the mcrr/mcrr2 instructions from the intrinsic was causing an assertion failure. This has now been fixed in llvm. llvm-svn: 272983
* Reverting r272777 because one of the testsRanjeet Singh2016-06-151-19/+7
| | | | | | | added in the llvm patch is causing an assertion to fail. llvm-svn: 272790
* [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.Ranjeet Singh2016-06-151-7/+19
| | | | | | | | | | | | | | Patch adds intrinsics for mrrc/mrrc2. The intrinsics for mrrc/mrrc2 return a single uint64_t to represent two 32 bit values. The mcrr/mcrr2 intrinsic was changed to accept a single uint64_t instead of two 32 bit values as the input for consistency. Differential Revision: http://reviews.llvm.org/D21179 llvm-svn: 272777
* [ARM] Add load/store co-processor intrinsics.Ranjeet Singh2016-05-311-0/+32
| | | | | | Differential Revision: http://reviews.llvm.org/D20563 llvm-svn: 271275
* [ARM] Fix cdp intrinsicRanjeet Singh2016-05-191-0/+12
| | | | | | | | | | | - Fixed cdp intrinsic to only accept compile time constant values previously you could pass in a variable to the builtin which would result in illegal llvm assembly output Differential Revision: http://reviews.llvm.org/D20394 llvm-svn: 270058
* [ARM] Mark mcr/mrc builtin operands as required-immediate.Ahmed Bougacha2015-08-261-0/+34
| | | | | | An early error message is better than the "cannot select" alternative. llvm-svn: 246094
* ARM: Add dbg builtin intrinsicYi Kong2014-08-261-1/+4
| | | | llvm-svn: 216452
* ARM: Prefetch intrinsicsYi Kong2014-08-131-0/+5
| | | | llvm-svn: 215568
* [ARM] Implement ISB memory barrier intrinsicYi Kong2014-07-031-0/+6
| | | | | | | Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212277
* Really fix the declaration of __clear_cache.Rafael Espindola2013-05-141-4/+4
| | | | | | | | | | | | | When I tested gcc's behaviour before, I forgot the extern "C", so it would warn when the types *did* match. So in the end * __clear_cache takes two void pointers. * aarch64 was correct before. * libgcc's manual is wrong. * this patch fixes arm. llvm-svn: 181810
* Fix __clear_cache on ARM.Rafael Espindola2013-05-141-9/+9
| | | | | | | | | | Current gcc's produce an error if __clear_cache is anything but __clear_cache(char *a, char *b); It looks like we had just implemented a gcc bug that is now fixed. llvm-svn: 181784
* Fix PR 11709: Change the definition of va_list to meet AAPCS requirementLogan Chien2012-10-101-1/+19
| | | | | | | | | | | | | AAPCS ABI Section 7.1.4 [1] specifies that va_list should be defined as struct __va_list { void *__ap;}; And in C++, it is defined in namespace std. [1] http://infocenter.arm.com/help/topic /com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf Patch by Weiming Zhao. llvm-svn: 165609
* __builtin_va_list is void* on ARM, not char*.John McCall2011-05-091-0/+5
| | | | | | rdar://problem/9391966 llvm-svn: 131080
* Builtins/ARM: __clear_cache doesn't seem to have a consistent prototype, declareDaniel Dunbar2010-07-161-0/+11
the builtin as void __clear_cache(...) to workaround this, which appears to match what GCC does. llvm-svn: 108487
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