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* [SystemZ] Add support for IBM z14 processor (2/3)Ulrich Weigand2017-07-171-1/+1
| | | | | | | | | | This patch extends the -fzvector language feature to enable the new "vector float" data type when compiling at -march=z14. This matches the updated extension definition implemented by other compilers for the platform, which is indicated to applications by pre-defining __VEC__ to 10302 (instead of 10301). llvm-svn: 308198
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-171-0/+19
| | | | | | | | | | | This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. Support for the -fzvector extension to vector float and the new high-level vector intrinsics is provided by separate patches. llvm-svn: 308197
* [X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs.Craig Topper2017-06-301-0/+2
| | | | | | Diffential Revision: https://reviews.llvm.org/D34842 llvm-svn: 306851
* [Clang][X86][Goldmont]Adding new target-cpu: Goldmont Michael Zuckerman2017-06-291-0/+73
| | | | | | | | | | | | | | | [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
* [X86][LWP] Add __LWP__ macro testsSimon Pilgrim2017-05-081-0/+8
| | | | | | | | Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
* When we turn on vsx it should also turn on altivec explicitly, sameEric Christopher2017-04-151-0/+8
| | | | | | | | | with disabling it as well as disabling all vsx specific features when turning off altivec. Fixes PR32663. llvm-svn: 300395
* Default enable the rtm feature only on skylake and later for now because ↵Eric Christopher2017-03-281-4/+0
| | | | | | | | | | Intel disabled the feature on some haswell and broadwell processors: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf the -mrtm option will still work normally. llvm-svn: 298956
* Turn on HTM on power8 and later (including powerpc64le) since it'sEric Christopher2017-03-201-0/+18
| | | | | | available by default on those cpus and configurations. llvm-svn: 298307
* [X86] Clzero flag addition and inclusion under znver1Craig Topper2017-02-091-0/+2
| | | | | | | | | | | | | 1. Adds the command line flag for clzero. 2. Includes the clzero flag under znver1. 3. Defines the macro for clzero. 4. Adds a new file which has the intrinsic definition for clzero instruction. Patch by Ganesh Gopalasubramanian with some additional tests from me. Differential revision: https://reviews.llvm.org/D29386 llvm-svn: 294559
* [X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and ↵Craig Topper2017-02-081-0/+2
| | | | | | __PREFETCHWT1__ define to match gcc. llvm-svn: 294424
* [X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc.Craig Topper2017-02-081-0/+6
| | | | llvm-svn: 294423
* [X86] Add -mmpx/-mno-mpx command line options and __MPX__ define to match gcc.Craig Topper2017-02-081-0/+6
| | | | llvm-svn: 294419
* [X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to ↵Craig Topper2017-02-081-0/+2
| | | | | | | | match gcc. In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file. llvm-svn: 294416
* [X86] Add -mclflushopt/-mno-clflushopt command line support and ↵Craig Topper2017-02-081-0/+8
| | | | | | __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
* [SystemZ] Provide predefined __ARCH__ and __VX__ macrosUlrich Weigand2017-02-061-23/+70
| | | | | | | | | | | | GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
* AMD family 17h (znver1) enablementCraig Topper2017-01-101-0/+82
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
* [SystemZ] Add -march=archX aliasesUlrich Weigand2016-10-311-0/+3
| | | | | | | | | | | | | | | For compatibility with other compilers on the platform, allow specifying levels of the z/Architecture instead of model names with -march. In particular, the following aliases are now supported: -march=arch8 equals -march=z10 -march=arch9 equals -march=z196 -march=arch10 equals -march=zEC12 -march=arch11 equals -march=z13 This parallels the equivalent (and prerequisite) LLVM change in r285577. llvm-svn: 285578
* [Power9] Builtins for ELF v.2 ABI conformance - front end portionNemanja Ivanovic2016-09-271-0/+6
| | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D24397 It adds the __POWER9_VECTOR__ macro and the -mpower9-vector option along with a number of altivec.h functions (refer to the code review for a list). llvm-svn: 282481
* [Myriad]: better compatibility with vendor sourceDouglas Katzman2016-07-251-0/+3
| | | | | | | | - Accept ma{2100,2150,2150} for -mcpu - Define more preprocessor macros - Don't append "le/" to little-endian lib dirs llvm-svn: 276646
* [X86] Introduction of -march=lakemont.Andrey Turetskiy2016-04-051-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D18651 llvm-svn: 265405
* Clean up a couple more preprocessor tests to use match-full-lines.James Y Knight2016-04-011-173/+173
| | | | llvm-svn: 265187
* Myriad: define __myriad2 macro automaticallyDouglas Katzman2016-03-151-1/+10
| | | | llvm-svn: 263596
* [X86] AMD Bobcat CPU (btver1) doesn't support XSAVE Simon Pilgrim2016-03-051-2/+0
| | | | | | | | btver1 is a SSSE3/SSE4a only CPU - it doesn't have AVX and doesn't support XSAVE. Differential Revision: http://reviews.llvm.org/D17682 llvm-svn: 262772
* [X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. ↵Craig Topper2016-02-291-0/+4
| | | | | | Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
* AMDGPU: Fix broken/confusing predefined macroMatt Arsenault2016-02-271-0/+14
| | | | | | amdgcn should not be defining __R600__ llvm-svn: 262124
* Added SKL and CNL processors and features to ClangElena Demikhovsky2016-02-211-2/+140
| | | | | | Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
* [SystemZ] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macrosUlrich Weigand2016-02-051-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_[1248] macros on SystemZ. This fixes a miscompile of GCC C++11 standard library headers due to use of those macros in an ABI-changing manner. See e.g. /usr/include/c++/4.8.5/ext/concurrence.h: // Compile time constant that indicates prefered locking policy in // the current configuration. static const _Lock_policy __default_lock_policy = #ifdef __GTHREADS #if (defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) \ && defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4)) _S_atomic; #else _S_mutex; #endif #else _S_single; #endif A different choice of __default_lock_policy causes different sizes of several of the C++11 data structures, which are then incompatible when inlined in clang-compiled code with what the (GCC-compiled) external library expects. This in turn leads to various crashes when using std::thread in code compiled with clang, as see e.g. via the ThreadPool unit tests. See PR 26473 for an example. llvm-svn: 259931
* Add the variant of __sparc_v9__ with five underscores, not just four.Joerg Sonnenberger2015-11-101-0/+3
| | | | llvm-svn: 252640
* Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8Joerg Sonnenberger2015-11-091-0/+9
| | | | | | | | | is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
* [X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro ↵Craig Topper2015-10-151-0/+44
| | | | | | defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
* [PowerPC] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros on all PPC coresHal Finkel2015-10-011-0/+3
| | | | | | | | | | | | We support all __sync_val_compare_and_swap_* builtins (only 64-bit on 64-bit targets) on all cores, and should define the corresponding __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros, just as GCC does. As it turns out, this is really important because they're needed to prevent a bad ODR violation with libstdc++'s std::shared_ptr (this is well explained in PR12730). We were doing this only for P8, but this is necessary on all PPC systems. llvm-svn: 249009
* Add support for System z vector language extensionsUlrich Weigand2015-07-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The z13 vector facility has an associated language extension, closely modeled on AltiVec/VSX. The main differences are: - vector long, vector float and vector pixel are not supported - vector long long and vector double are supported (like VSX) - comparison operators return a vector rather than a scalar integer - shift operators behave like the OpenCL shift operators - vector bool is only supported as argument to certain operators; some operators allow mixing a bool with a non-bool vector This patch adds clang support for the extension. It is closely modelled on the AltiVec support. Similarly to the -faltivec option, there's a new -fzvector option to enable the extensions (as well as an -mzvector alias for compatibility with GCC). There's also a separate LangOpt. The extension as implemented here is intended to be compatible with the -mzvector extension recently implemented by GCC. Based on a patch by Richard Sandiford. Differential Revision: http://reviews.llvm.org/D11001 llvm-svn: 243642
* Testing for the fix for bug 23429.Nemanja Ivanovic2015-05-141-0/+13
| | | | | | | | | Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
* [Sparc] Add support for 'sparcel' to clang.Douglas Katzman2015-05-111-0/+33
| | | | | | Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
* [SystemZ] Support transactional execution on zEC12Ulrich Weigand2015-04-011-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
* Add Clang support for PPC cryptography builtinsNemanja Ivanovic2015-03-041-0/+6
| | | | | | Review: http://reviews.llvm.org/D7951 llvm-svn: 231291
* [X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add ↵Andrea Di Biagio2014-11-061-0/+10
| | | | | | | | | | | | | | | | | | | missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
* [PowerPC] Add feature for Power8 vector extensionsBill Schmidt2014-10-101-0/+7
| | | | | | | | | | | | | | | | | | The current VSX feature for PowerPC specifies availability of the VSX instructions added with the 2.06 architecture version. With 2.07, the architecture adds new instructions to both the Category:Vector and Category:VSX instruction sets. Additionally, unaligned vector storage operations have improved performance. This patch adds a feature to provide access to the new instructions and performance capabilities of Power8. For compatibility with GCC, the feature is controlled via a new -mpower8-vector switch, and the feature causes the __POWER8_VECTOR__ builtin define to be generated by the preprocessor. There is a companion patch for llvm being committed at the same time. llvm-svn: 219502
* [x86] Enable broadwell target in clang.Robert Khasanov2014-09-191-0/+64
| | | | | | Added -madx option llvm-svn: 218116
* [SKX] Enabling SKX target (Skylake server chip) Robert Khasanov2014-07-301-0/+72
| | | | | | | | | a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
* Add support for -march=bdver4.Benjamin Kramer2014-05-021-0/+70
| | | | llvm-svn: 207848
* Driver: Add support for -march=bdver3 on x86.Benjamin Kramer2013-11-041-0/+66
| | | | llvm-svn: 193985
* Add preprocessor support for powerpc vsx.Eric Christopher2013-10-161-0/+7
| | | | | | The test should be expanded upon for more powerpc checking. llvm-svn: 192849
* Remove an old, seemingly out of date, comment.Eric Christopher2013-10-161-3/+0
| | | | | | The referenced script no longer seems to exist. llvm-svn: 192848
* Enabling 3DNow! prefetch instruction support for a few AMD processors in theYunzhong Gao2013-10-161-0/+8
| | | | | | | | | | clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
* Adding -mtbm and -mno-tbm command line options to the clang front end for theYunzhong Gao2013-09-241-0/+2
| | | | | | | | | x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
* Add support for -march=slm, aka Intel Atom Silvermont.Benjamin Kramer2013-08-301-0/+36
| | | | llvm-svn: 189670
* Add avx512cd, avx512er, avx512pf feature flags and enable them on KNL CPU.Craig Topper2013-08-211-0/+6
| | | | llvm-svn: 188867
* Rename __AVX512__ to __AVX512F__Craig Topper2013-08-201-2/+2
| | | | llvm-svn: 188764
* Add AVX-512 feature flag and knl cpu to clang.Craig Topper2013-08-201-0/+64
| | | | llvm-svn: 188758
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