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* [X86] Disable CLWB in Cannon LakeCraig Topper2018-02-211-2/+2
| | | | | | | | | | | Cannon Lake does not support CLWB, therefore it does not include all features listed under SKX. Patch by Gabor Buella Differential Revision: https://reviews.llvm.org/D43459 llvm-svn: 325655
* [Myriad] Define __ma2x5x and __ma2x8xWalter Lee2018-02-061-0/+4
| | | | | | | | | | | | Summary: Add architecture defines for ma2x5x and ma2x8x. Reviewers: jyknight Subscribers: fedor.sergeev, MartinO Differential Revision: https://reviews.llvm.org/D42882 llvm-svn: 324420
* [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.Craig Topper2018-01-261-0/+2
| | | | | | gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546 llvm-svn: 323552
* [X86] Add rdpid command line option and intrinsics.Craig Topper2018-01-201-0/+2
| | | | | | | | | | | | | | Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made. Reviewers: RKSimon, spatel, zvi, AndreiGrischenko Reviewed By: RKSimon Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D42272 llvm-svn: 323047
* [X86] Add missing check for RDSEED to ICL, CNL, SKX sections of ↵Craig Topper2018-01-191-0/+6
| | | | | | test/Preprocessor/predefined-arch-macros.c llvm-svn: 322912
* Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and ↵Craig Topper2017-12-291-6/+6
| | | | | | | | | | | | | | icelake or CLWB on cannonlake." I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Which specifically said CLWB wasn't until Icelake. But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe. I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing. llvm-svn: 321547
* [X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on ↵Craig Topper2017-12-271-0/+6
| | | | | | | | cannonlake. We have cannonlake and icelake inheriting from skylake server in a switch using fallthroughs. But they aren't perfect supersets of skylake server. llvm-svn: 321504
* [X86] Test that -march=skx enables PKU.Craig Topper2017-12-271-0/+2
| | | | llvm-svn: 321503
* [X86] Enable avx512vpopcntdq and clwb for icelake.Craig Topper2017-12-271-0/+4
| | | | | | Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference llvm-svn: 321502
* [x86][icelake][vbmi2]Coby Tayree2017-12-271-0/+2
| | | | | | | | | | | | | | | added vbmi2 feature recognition added intrinsics support for vbmi2 instructions _mm[128,256,512]_mask[z]_compress_epi[16,32] _mm[128,256,512]_mask_compressstoreu_epi[16,32] _mm[128,256,512]_mask[z]_expand_epi[16,32] _mm[128,256,512]_mask[z]_expandloadu_epi[16,32] _mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64] _mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64] matching a similar work on the backend (D40206) Differential Revision: https://reviews.llvm.org/D41557 llvm-svn: 321487
* [x86][icelake][vnni]Coby Tayree2017-12-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added vnni feature recognition added intrinsics support for VNNI instructions _mm256_mask_dpbusd_epi32 _mm256_maskz_dpbusd_epi32 _mm256_dpbusd_epi32 _mm256_mask_dpbusds_epi32 _mm256_maskz_dpbusds_epi32 _mm256_dpbusds_epi32 _mm256_mask_dpwssd_epi32 _mm256_maskz_dpwssd_epi32 _mm256_dpwssd_epi32 _mm256_mask_dpwssds_epi32 _mm256_maskz_dpwssds_epi32 _mm256_dpwssds_epi32 _mm128_mask_dpbusd_epi32 _mm128_maskz_dpbusd_epi32 _mm128_dpbusd_epi32 _mm128_mask_dpbusds_epi32 _mm128_maskz_dpbusds_epi32 _mm128_dpbusds_epi32 _mm128_mask_dpwssd_epi32 _mm128_maskz_dpwssd_epi32 _mm128_dpwssd_epi32 _mm128_mask_dpwssds_epi32 _mm128_maskz_dpwssds_epi32 _mm128_dpwssds_epi32 _mm512_mask_dpbusd_epi32 _mm512_maskz_dpbusd_epi32 _mm512_dpbusd_epi32 _mm512_mask_dpbusds_epi32 _mm512_maskz_dpbusds_epi32 _mm512_dpbusds_epi32 _mm512_mask_dpwssd_epi32 _mm512_maskz_dpwssd_epi32 _mm512_dpwssd_epi32 _mm512_mask_dpwssds_epi32 _mm512_maskz_dpwssds_epi32 _mm512_dpwssds_epi32 matching a similar work on the backend (D40208) Differential Revision: https://reviews.llvm.org/D41558 llvm-svn: 321484
* [x86][icelake][bitalg]Coby Tayree2017-12-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added bitalg feature recognition added intrinsics support for bitalg instructions _mm512_popcnt_epi16 _mm512_mask_popcnt_epi16 _mm512_maskz_popcnt_epi16 _mm512_popcnt_epi8 _mm512_mask_popcnt_epi8 _mm512_maskz_popcnt_epi8 _mm512_mask_bitshuffle_epi64_mask _mm512_bitshuffle_epi64_mask _mm256_popcnt_epi16 _mm256_mask_popcnt_epi16 _mm256_maskz_popcnt_epi16 _mm128_popcnt_epi16 _mm128_mask_popcnt_epi16 _mm128_maskz_popcnt_epi16 _mm256_popcnt_epi8 _mm256_mask_popcnt_epi8 _mm256_maskz_popcnt_epi8 _mm128_popcnt_epi8 _mm128_mask_popcnt_epi8 _mm128_maskz_popcnt_epi8 _mm256_mask_bitshuffle_epi32_mask _mm256_bitshuffle_epi32_mask _mm128_mask_bitshuffle_epi16_mask _mm128_bitshuffle_epi16_mask matching a similar work on the backend (D40222) Differential Revision: https://reviews.llvm.org/D41564 llvm-svn: 321483
* [x86][icelake][vpclmulqdq]Coby Tayree2017-12-271-0/+2
| | | | | | | | | | | added vpclmulqdq feature recognition added intrinsics support for vpclmulqdq instructions _mm256_clmulepi64_epi128 _mm512_clmulepi64_epi128 matching a similar work on the backend (D40101) Differential Revision: https://reviews.llvm.org/D41573 llvm-svn: 321480
* [x86][icelake][gfni]Coby Tayree2017-12-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | added gfni feature recognition added intrinsics support for gfni instructions _mm_gf2p8affineinv_epi64_epi8 _mm_mask_gf2p8affineinv_epi64_epi8 _mm_maskz_gf2p8affineinv_epi64_epi8 _mm256_gf2p8affineinv_epi64_epi8 _mm256_mask_gf2p8affineinv_epi64_epi8 _mm256_maskz_gf2p8affineinv_epi64_epi8 _mm512_gf2p8affineinv_epi64_epi8 _mm512_mask_gf2p8affineinv_epi64_epi8 _mm512_maskz_gf2p8affineinv_epi64_epi8 _mm_gf2p8affine_epi64_epi8 _mm_mask_gf2p8affine_epi64_epi8 _mm_maskz_gf2p8affine_epi64_epi8 _mm256_gf2p8affine_epi64_epi8 _mm256_mask_gf2p8affine_epi64_epi8 _mm256_maskz_gf2p8affine_epi64_epi8 _mm512_gf2p8affine_epi64_epi8 _mm512_mask_gf2p8affine_epi64_epi8 _mm512_maskz_gf2p8affine_epi64_epi8 _mm_gf2p8mul_epi8 _mm_mask_gf2p8mul_epi8 _mm_maskz_gf2p8mul_epi8 _mm256_gf2p8mul_epi8 _mm256_mask_gf2p8mul_epi8 _mm256_maskz_gf2p8mul_epi8 _mm512_gf2p8mul_epi8 _mm512_mask_gf2p8mul_epi8 _mm512_maskz_gf2p8mul_epi8 matching a similar work on the backend (D40373) Differential Revision: https://reviews.llvm.org/D41582 llvm-svn: 321477
* [x86][icelake][vaes]Coby Tayree2017-12-271-0/+2
| | | | | | | | | | | | | | | added vaes feature recognition added intrinsics support for vaes instructions, matching a similar work on the backend (D40078) _mm256_aesenc_epi128 _mm512_aesenc_epi128 _mm256_aesenclast_epi128 _mm512_aesenclast_epi128 _mm256_aesdec_epi128 _mm512_aesdec_epi128 _mm256_aesdeclast_epi128 _mm512_aesdeclast_epi128 llvm-svn: 321474
* [X86] Add missing check lines for the silvermont cases in ↵Craig Topper2017-12-221-0/+8
| | | | | | predefined-arch-macros.c test. llvm-svn: 321343
* [X86] Add 'prfchw' to the correct CPUs to match the backend.Craig Topper2017-12-221-0/+18
| | | | llvm-svn: 321341
* [X86] Add icelake CPU support for -march.Craig Topper2017-11-191-0/+89
| | | | llvm-svn: 318617
* [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake.Craig Topper2017-11-191-6/+12
| | | | | | This is the resolution we came to in D38824. llvm-svn: 318616
* [X86] Define i586 and pentium preprocessor defines for -march=lakemont to ↵Craig Topper2017-11-011-7/+11
| | | | | | match GCC llvm-svn: 317069
* [X86] Make -march=i686 an alias of -march=pentiumproCraig Topper2017-10-261-0/+2
| | | | | | | | I think the only reason they are different is because we don't set tune_i686 for -march=i686 to match GCC. But GCC 4.9.0 seems to have changed this behavior and they do set it now. So I think they can aliases now. Differential Revision: https://reviews.llvm.org/D39349 llvm-svn: 316712
* [X86] Add avx512vpopcntdq to Knights MillCraig Topper2017-10-251-0/+2
| | | | | | As indicated by Table 1-1 in Intel Architecture Instruction Set Extensions and Future Features Programming Reference from October 2017. llvm-svn: 316593
* AMDGPU: Parse r600 CPU name early and expose FMAF capabilityJan Vesely2017-10-191-0/+10
| | | | | | | Improve amdgcn macro test Differential Revision: https://reviews.llvm.org/D38667 llvm-svn: 316181
* [X86] Remove 'knm' defines from predefined-arch-macros.c test.Craig Topper2017-10-131-6/+0
| | | | | | Direction seems to be that we dont' want to keep adding these, but I forgot to remove it from the test before I committed r315723. llvm-svn: 315729
* [X86] Add skeleton support for knm cpuCraig Topper2017-10-131-0/+75
| | | | | | | | This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation. Differential Revision: https://reviews.llvm.org/D38813 llvm-svn: 315723
* [X86] Remove a few unnecessary check lines from the predefined-arch-macros test.Craig Topper2017-10-121-16/+0
| | | | | | These were testing OS macros and clang/llvm macros. llvm-svn: 315547
* Add support for Myriad ma2x8x series of CPUsWalter Lee2017-10-021-5/+45
| | | | | | | | | | | | | | | Summary: Also: - Add support for some older Myriad CPUs that were missing. - Fix some incorrect compiler defines for exisitng CPUs. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37551 llvm-svn: 314706
* [Clang] Adding missing feature to goldmontMichael Zuckerman2017-09-251-0/+2
| | | | | Change-Id: I6c22478d16b8e02ce60dae2f8c80d43bc5ab3a9c llvm-svn: 314104
* [SystemZ] Add support for IBM z14 processor (2/3)Ulrich Weigand2017-07-171-1/+1
| | | | | | | | | | This patch extends the -fzvector language feature to enable the new "vector float" data type when compiling at -march=z14. This matches the updated extension definition implemented by other compilers for the platform, which is indicated to applications by pre-defining __VEC__ to 10302 (instead of 10301). llvm-svn: 308198
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-171-0/+19
| | | | | | | | | | | This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. Support for the -fzvector extension to vector float and the new high-level vector intrinsics is provided by separate patches. llvm-svn: 308197
* [X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs.Craig Topper2017-06-301-0/+2
| | | | | | Diffential Revision: https://reviews.llvm.org/D34842 llvm-svn: 306851
* [Clang][X86][Goldmont]Adding new target-cpu: Goldmont Michael Zuckerman2017-06-291-0/+73
| | | | | | | | | | | | | | | [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 llvm-svn: 306673
* [X86][LWP] Add __LWP__ macro testsSimon Pilgrim2017-05-081-0/+8
| | | | | | | | Missed in rL302418 Differential Revision: https://reviews.llvm.org/D32770 llvm-svn: 302445
* When we turn on vsx it should also turn on altivec explicitly, sameEric Christopher2017-04-151-0/+8
| | | | | | | | | with disabling it as well as disabling all vsx specific features when turning off altivec. Fixes PR32663. llvm-svn: 300395
* Default enable the rtm feature only on skylake and later for now because ↵Eric Christopher2017-03-281-4/+0
| | | | | | | | | | Intel disabled the feature on some haswell and broadwell processors: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf the -mrtm option will still work normally. llvm-svn: 298956
* Turn on HTM on power8 and later (including powerpc64le) since it'sEric Christopher2017-03-201-0/+18
| | | | | | available by default on those cpus and configurations. llvm-svn: 298307
* [X86] Clzero flag addition and inclusion under znver1Craig Topper2017-02-091-0/+2
| | | | | | | | | | | | | 1. Adds the command line flag for clzero. 2. Includes the clzero flag under znver1. 3. Defines the macro for clzero. 4. Adds a new file which has the intrinsic definition for clzero instruction. Patch by Ganesh Gopalasubramanian with some additional tests from me. Differential revision: https://reviews.llvm.org/D29386 llvm-svn: 294559
* [X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and ↵Craig Topper2017-02-081-0/+2
| | | | | | __PREFETCHWT1__ define to match gcc. llvm-svn: 294424
* [X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc.Craig Topper2017-02-081-0/+6
| | | | llvm-svn: 294423
* [X86] Add -mmpx/-mno-mpx command line options and __MPX__ define to match gcc.Craig Topper2017-02-081-0/+6
| | | | llvm-svn: 294419
* [X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to ↵Craig Topper2017-02-081-0/+2
| | | | | | | | match gcc. In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file. llvm-svn: 294416
* [X86] Add -mclflushopt/-mno-clflushopt command line support and ↵Craig Topper2017-02-081-0/+8
| | | | | | __CLFLUSHOPT__ define to match gcc. llvm-svn: 294411
* [SystemZ] Provide predefined __ARCH__ and __VX__ macrosUlrich Weigand2017-02-061-23/+70
| | | | | | | | | | | | GCC 7 will predefine two new macros on s390x: - __ARCH__ indicates the ISA architecture level - __VX__ indicates that the vector facility is available This adds those macros to clang as well to ensure continued compatibility with GCC. llvm-svn: 294197
* AMD family 17h (znver1) enablementCraig Topper2017-01-101-0/+82
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
* [SystemZ] Add -march=archX aliasesUlrich Weigand2016-10-311-0/+3
| | | | | | | | | | | | | | | For compatibility with other compilers on the platform, allow specifying levels of the z/Architecture instead of model names with -march. In particular, the following aliases are now supported: -march=arch8 equals -march=z10 -march=arch9 equals -march=z196 -march=arch10 equals -march=zEC12 -march=arch11 equals -march=z13 This parallels the equivalent (and prerequisite) LLVM change in r285577. llvm-svn: 285578
* [Power9] Builtins for ELF v.2 ABI conformance - front end portionNemanja Ivanovic2016-09-271-0/+6
| | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D24397 It adds the __POWER9_VECTOR__ macro and the -mpower9-vector option along with a number of altivec.h functions (refer to the code review for a list). llvm-svn: 282481
* [Myriad]: better compatibility with vendor sourceDouglas Katzman2016-07-251-0/+3
| | | | | | | | - Accept ma{2100,2150,2150} for -mcpu - Define more preprocessor macros - Don't append "le/" to little-endian lib dirs llvm-svn: 276646
* [X86] Introduction of -march=lakemont.Andrey Turetskiy2016-04-051-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D18651 llvm-svn: 265405
* Clean up a couple more preprocessor tests to use match-full-lines.James Y Knight2016-04-011-173/+173
| | | | llvm-svn: 265187
* Myriad: define __myriad2 macro automaticallyDouglas Katzman2016-03-151-1/+10
| | | | llvm-svn: 263596
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