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* AArch64: add missing Apple CPU names and use them by default.Tim Northover2020-01-081-4/+17
| | | | | | | | Apple's CPUs are called A7-A13 in official communication, occasionally with weird suffixes which we probably don't need to care about. This adds each one and describes its features. It also switches the default CPU to the canonical name for Cyclone, but leaves legacy support in so that existing bitcode still compiles.
* AArch64: add arm64_32 support to Clang.Tim Northover2019-11-121-0/+3
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* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-2/+0
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* [AArch64] Disable __ARM_FEATURE_SVE without ACLE.Sander de Smalen2019-07-301-1/+1
| | | | | | | | | | | | | | | | | The Arm C Language Extensions for SVE document specifies that __ARM_FEATURE_SVE should be set when the compiler supports SVE and implements all the extensions described in the document. This is currently not yet the case, so the feature should be disabled until the compiler can provide all the extensions as described. Reviewers: c-rhodes, rengolin, rovka, ktkachov Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D65404 llvm-svn: 367301
* [AArch64] Add support for MTE intrinsicsJaved Absar2019-04-261-0/+3
| | | | | | | | | | | | This provides intrinsics support for Memory Tagging Extension (MTE), which was introduced with the Armv8.5-a architecture. These intrinsics are available when __ARM_FEATURE_MEMORY_TAGGING is defined. Each intrinsic is described in detail in the ACLE Q1 2019 documentation: https://developer.arm.com/docs/101028/latest Reviewed By: Tim Nortover, David Spickett Differential Revision: https://reviews.llvm.org/D60485 llvm-svn: 359348
* [clang] Add support for Exynos M5 (NFC)Evandro Menezes2019-03-221-0/+1
| | | | | | Add Exynos M5 test cases. llvm-svn: 356794
* [test] Update support for Exynos M4 (NFC)Evandro Menezes2019-01-111-1/+2
| | | | | | Update test cases for Exynos M4. llvm-svn: 350954
* [AArch64] Implement FP16FML intrinsicsBryan Chan2018-10-251-12/+18
| | | | | | | | | | | | | Generate the FP16FML intrinsics into arm_neon.h (AArch64 only for now). Add two new type modifiers to NeonEmitter to handle the new prototypes. Define __ARM_FEATURE_FP16FML when +fp16fml is enabled and guard the intrinsics with the macro in arm_neon.h. Based on a patch by Gao Yiling. Differential Revision: https://reviews.llvm.org/D53633 llvm-svn: 345344
* [AArch64][ARM] Context sensitive meaning of cryptoSjoerd Meijer2018-10-041-0/+95
| | | | | | | | | | | | | | For AArch64, crypto means: - sm4 + sha3 + sha2 + aes for Armv8.4-A and up, and - sha2 + aes for Armv8.3-A and earlier. For AArch32: Crypto means sha2 + aes, because the Armv8.2-A crypto instructions were added to AArch64 only. Differential Revision: https://reviews.llvm.org/D50179 llvm-svn: 343758
* [ARM][AArch64] Add feature +fp16fmlSjoerd Meijer2018-09-241-2/+29
| | | | | | | | | | | | | | | | | | | | | Armv8.4-A adds a few FP16 instructions that can optionally be implemented in CPUs of Armv8.2-A and above. This patch adds a feature to clang to permit selection of these instructions. This interacts with the +fp16 option as follows: Prior to Armv8.4-A: *) +fp16fml implies +fp16 *) +nofp16 implies +nofp16fml From Armv8.4-A: *) The above conditions apply, additionally: +fp16 implies +fp16fml Patch by Bernard Ogden. Differential Revision: https://reviews.llvm.org/D50229 llvm-svn: 342862
* [PATCH 2/2] [test] Add support for Samsung Exynos M4 (NFC)Evandro Menezes2018-06-061-0/+1
| | | | | | Add test cases for Exynos M4. llvm-svn: 334116
* [AAch64] Add the __ARM_FEATURE_DOTPROD macro definitionJunmo Park2018-04-171-0/+4
| | | | | | | | | This matches what GCC does. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/aarch64/aarch64-c.c Differential Revision: https://reviews.llvm.org/D45544 llvm-svn: 330229
* [AAch64] Tests for ACLE FP16 macrosSjoerd Meijer2018-03-151-0/+12
| | | | | | | | This adds some missing tests for the AArch64 FP16 macros. Differential Revision: https://reviews.llvm.org/D44512 llvm-svn: 327623
* [AArch64] Add support for handling the +sve target feature.Amara Emerson2017-07-131-0/+5
| | | | | | | | This also adds the appropriate predefine for SVE if enabled. Differential Revision: https://reviews.llvm.org/D35118 llvm-svn: 307919
* ARMV8-A archkind and target defines helper functionsSjoerd Meijer2017-06-301-2/+3
| | | | | | | | | | | | This introduces helper functions that set target defines for different ARMV8-A architecture kinds. It fixes an issue that the v8.1 define ARM_FEATURE_QRDMX was not set for v8.2. These helper functions make things more “scalable” if we want to add ARMv8.3 at some point, and a cleanup has been done to hold the architecture kind in one variable (instead of one for each). Differential Revision: https://reviews.llvm.org/D34686 llvm-svn: 306805
* [Driver] Update AArch64 testcase to match llvm r302078.Ahmed Bougacha2017-05-031-1/+1
| | | | llvm-svn: 302079
* [AArch64] Vulcan is now ThunderXT99Joel Jones2017-03-071-2/+2
| | | | | | | | | | | | | Broadcom Vulcan is now Cavium ThunderX2T99. LLVM Bugzilla: http://bugs.llvm.org/show_bug.cgi?id=32113 Corresponding LLVM change: https://reviews.llvm.org/rL297190 Changes to clang to support the change. Patch by Joel Jones llvm-svn: 297227
* Add support for Samsung Exynos M3 (NFC)Evandro Menezes2016-12-131-0/+1
| | | | llvm-svn: 289614
* [AArch64] Add support for Samsung Exynos M2 (NFC).Evandro Menezes2016-08-011-0/+1
| | | | llvm-svn: 277365
* [Driver][AArch64] Add support for Broadcom Vulcan core.Pankaj Gode2016-06-291-0/+2
| | | | | | | | Adding support for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21501 llvm-svn: 274114
* This adds target support and tests for Cortex-A73Sjoerd Meijer2016-06-021-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D20864 llvm-svn: 271507
* Revert "[AArch64] Using new TargetParser in Clang"Renato Golin2016-05-251-4/+1
| | | | | | | | This reverts commit r270688 and r270689. The issue is not a random order, but a different order for some targets and others (prob. Linux vs Darwin). Reverting until we have a better fix. llvm-svn: 270691
* [AArch64] Try to fix test from r270688 with unordered outputRenato Golin2016-05-251-1/+4
| | | | llvm-svn: 270689
* AArch64: fix Cyclone CPU features list.Tim Northover2016-02-241-3/+3
| | | | | | It turns out we don't have CRC after all. Who knew? llvm-svn: 261758
* [Driver] Add support for Qualcomm's Kryo CPU.Chad Rosier2016-02-111-0/+2
| | | | | | http://reviews.llvm.org/D17124 llvm-svn: 260555
* [AArch64] Teaches clang about Samsung Exynos-M1MinSeong Kim2016-01-051-0/+2
| | | | | | | | Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15664 llvm-svn: 256829
* Teaches clang about Cortex-A35.Christof Douma2015-12-021-0/+2
| | | | | | | | Adds support for the new Cortex-A35 ARMv8-A core. Differential Revision: http://reviews.llvm.org/D15142 llvm-svn: 254505
* ARM v8.1a adds Advanced SIMD instructions for Rounding Double MultiplyAlexandros Lamprineas2015-11-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Add/Subtract. The following instructions are added to AArch32 instruction set: - VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half - VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half The following instructions are added to AArch64 instruction set: - SQRDMLAH: Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half - SQRDMLSH: Signed Saturating Rounding Doubling Multiply Subtract Returning High Half This patch adds intrinsic and ACLE macro support for these instructions, as well as corresponding tests. Differential Revision: http://reviews.llvm.org/D14982 llvm-svn: 254250
* Implement ACLE 2.0 macros of chapters 6.6 and 6.7 for [ARM] and [Aarch64] ↵Alexandros Lamprineas2015-10-021-1/+5
| | | | | | | | targets. Differential Revision: http://reviews.llvm.org/D12633 llvm-svn: 249140
* Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] ↵Alexandros Lamprineas2015-09-031-3/+14
| | | | | | | | | targets. Differential Revision: http://reviews.llvm.org/D12244 Change-Id: Iffd4e822c15e18668fe8868278230ff232ef50aa llvm-svn: 246768
* [AArch64] Define the macro __ARM_FP16_ARGSKeith Walker2015-08-241-0/+1
| | | | | | | | | | | | | The ACLE (ARM C Language Extensions) 2.0 defines that the predefined macro __ARM_FP16_ARGS should be defined if __fp16 can be used as an argument and result. The support for __fp16 to be used as an argument and result is already implemented for AArch64 so this change is just adding the missing macro. Differential Revision: http://reviews.llvm.org/D12240 llvm-svn: 245833
* Allow case-insensitive values for -mtune for AArch64 target in line with GCC.Gabor Ballabas2015-07-201-0/+5
| | | | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -mtune option for the AArch64 target. Differential Revision: http://reviews.llvm.org/D10563 llvm-svn: 242663
* Allow case-insensitive values for -march for AArch64 target in line with GCC.Gabor Ballabas2015-06-181-0/+4
| | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -march option for the AArch64 target. llvm-svn: 240019
* Allow case-insensitive values for -mcpu for AArch64 target in line with GCC.Gabor Ballabas2015-06-121-0/+6
| | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -mcpu option for the AArch64 target. llvm-svn: 239619
* [AArch64] Add v8.1a architectureVladimir Sukharev2015-04-161-0/+8
| | | | | | | | | | | | Add support for AArch64 v8.1 architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8493 llvm-svn: 235110
* Teaches the Clang driver to accept Cortex-A72Renato Golin2015-02-041-0/+2
| | | | | | | | | A previous commit added Cortex-A72 to LLVM, this teaches Clang to accept it as well. Patch by Ranjeet Singh. llvm-svn: 228141
* AArch64: set all processor features from -arch if nothing else presentTim Northover2014-11-101-0/+3
| | | | | | | | | | Darwin's "-arch arm64" option implies full Cyclone CPU, for both architectural and tuning purposes. So if neither of the explicit options have been given, forward that on to the proper invocation. rdar://problem/18906227 llvm-svn: 221631
* [ARM] Add ACLE predefines: maxmin, rounding and h/w integer divisionJames Molloy2014-09-151-0/+3
| | | | | | Patch by Assad Hashmi! llvm-svn: 217760
* [AArch64] Implement Clang CLI interface proposal about "-march".Kevin Qin2014-07-181-11/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Revert "Add default feature for CPUs on AArch64 target in Clang" at r210625. Then, all enabled feature will by passed explicitly by -target-feature in -cc1 option. 2. Get "-mfpu" deprecated. 3. Implement support of "-march". Usage is: -march=armv8-a+[no]feature For instance, "-march=armv8-a+neon+crc+nocrypto". Here "armv8-a" is necessary, and CPU names are not acceptable. Candidate features are fp, neon, crc and crypto. Where conflicting feature modifiers are specified, the right-most feature is used. 4. Implement support of "-mtune". Usage is: -march=CPU_NAME For instance, "-march=cortex-a57". This option will ONLY get micro-architectural feature enabled specifying to target CPU, like "+zcm" and "+zcz" for cyclone. Any architectural features WON'T be modified. 5. Change usage of "-mcpu" to "-mcpu=CPU_NAME+[no]feature", which is an alias to "-march={feature of CPU_NAME}+[no]feature" and "-mtune=CPU_NAME" together. Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option. llvm-svn: 213353
* [AArch64] Add default features for CPUs on AArch64 target.Kevin Qin2014-06-111-0/+10
| | | | | | | | | | For ARM target, we can use CRYPTO and CRC features if we select cortex-a57 by '-mcpu', but for AArch64 target, it doesn't work unless adding with '-mfpu=crypto-neon-fp-armv8'. To keep consistency between front-end and back-end and get end-users more easier to use, we'd better add default feature for CPUs on AArch64 target as well. llvm-svn: 210625
* [ARM64/AArch64] Define the correct value for __ARM_NEON_FPBradley Smith2014-05-021-2/+7
| | | | llvm-svn: 207842
* [ARM64/AArch64] Hook up CRC32 subtarget feature to the driverBradley Smith2014-05-021-0/+5
| | | | llvm-svn: 207841
* [ARM64] Add ARM64 RUN lines to a bunch of tests that had AARCH64 RUN lines.James Molloy2014-04-171-0/+1
| | | | | | | This covers all tests in tests/Driver and tests/Preprocessor, but there are some failing tests in test/Sema that need looking into. llvm-svn: 206464
* Enable AArch64 NEON by default.Jiangning Liu2014-02-141-2/+2
| | | | llvm-svn: 201384
* Clean up predefined macros for AArch64 to follow ACLE 2.0.Jiangning Liu2013-11-191-14/+19
| | | | llvm-svn: 195068
* AArch64: initial NEON supportTim Northover2013-08-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187568
* AArch64: bring predefines in line with most recent ACLE documentTim Northover2013-04-051-17/+19
| | | | | | | | | | | The prefixes and names used are now identical to 32-bit ARM, which is also expected to remain unchanged. If we made this change after a release, we'd probably have to support both variants for a while, but I think since AArch64 exists only on trunk now, it's acceptable to simply swap them now. llvm-svn: 178870
* Add support for AArch64 target.Tim Northover2013-01-311-0/+30
In cooperation with the LLVM patch, this should implement all scalar front-end parts of the C and C++ ABIs for AArch64. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174055
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