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* [X86] AMD znver2 enablementGanesh Gopalasubramanian2019-02-261-0/+1
| | | | | | | | | | | | | | | | | This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
* [X86] Split up -march=icelake to -client & -serverGabor Buella2018-04-101-1/+2
| | | | | | | | | | Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
* [X86] Make sure 'knm' is accepted by -target-cpuCraig Topper2017-11-191-0/+1
| | | | llvm-svn: 318620
* [X86] Add icelake CPU support for -march.Craig Topper2017-11-191-0/+1
| | | | llvm-svn: 318617
* [X86] Add recent CPU strings to some of the tests that check other cpu names.Craig Topper2017-01-101-0/+5
| | | | llvm-svn: 291545
* AMD family 17h (znver1) enablementCraig Topper2017-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
* Don't actually generate code for testing the frontend's target cpu flag,Chandler Carruth2014-12-091-26/+28
| | | | | | | just verify. This should fix the bots where the x86 backend isn't built into Clang. Sorry for the breakage. llvm-svn: 223779
* Re-work the Clang system for classifying Intel x86 CPUs to use theirChandler Carruth2014-12-091-0/+28
basic microarchitecture names, and add support (with tests) for parsing all of the masic microarchitecture names for CPUs documented to be accepted by GCC with -march. I didn't go back through the 32-bit-only old microarchitectures, but this at least brings the recent architecture names up to speed. This is essentially the follow-up to the LLVM commit r223769 which did similar cleanups for the LLVM CPUs. One particular benefit is that you can now use -march=westmere in Clang and get the LLVM westmere processor which is a different ISA variant (!) and so quite significant. Much like with r223769, I would appreciate the Intel folks carefully thinking about the macros defined, names used, etc for the atom chips and newest primary x86 chips. The current patterns seem quite strange to me, especially here in Clang. Note that I haven't replicated the per-microarchitecture macro defines provided by GCC. I'm really opposed to source code using these rather than using ISA feature macros. llvm-svn: 223776
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