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* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-16/+0
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* [FIX] Change test to read file insteadDiogo N. Sampaio2019-05-091-1/+1
| | | | | | | | This should fix the test file failing in windows by reading the file it self instead of stdin, from 543913c3b41f llvm-svn: 360329
* [ARM] Fix the extensions implied by a cpu nameDiogo N. Sampaio2019-05-091-16/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When using `clang -mcpu=CPUNAME+FEATURELIST`, the implied features defined by CPUNAME are not obtained, as the entire string is passed. This fixes that by spiting the cpuname string in the first `+`, if any. For example, when using ```clang -### --target=arm-arm-none-eabi -march=armv7-a -mcpu=cortex-a8+nocrc``` the intrinsic ```"target-feature" "+dsp"``` implied by `cortex-a8` is missing. Reviewers: keith.walker.arm, DavidSpickett, carwil Reviewed By: DavidSpickett Subscribers: javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D61668 llvm-svn: 360324
* [clang] Add support for Exynos M5 (NFC)Evandro Menezes2019-03-221-0/+8
| | | | | | Add Exynos M5 test cases. llvm-svn: 356794
* [ARM] Add Cortex-M35P SupportLuke Cheeseman2019-03-221-2/+4
| | | | | | | | - Add clang frontend testing for Cortex-M35P Differential Revision: https://reviews.llvm.org/D57765 llvm-svn: 356742
* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-251-0/+34
| | | | | | | | | | - Add LLVM backend support for Cortex-A76 and Cortex-A76AE - Documentation can be found at https://developer.arm.com/products/processors/cortex-a/cortex-a76 Differential Revision: https://reviews.llvm.org/D57764 llvm-svn: 354789
* [test] Update support for Exynos M4 (NFC)Evandro Menezes2019-01-111-13/+17
| | | | | | Update test cases for Exynos M4. llvm-svn: 350954
* [ARM] Alter test to account for change to armv6k default CPUPeter Smith2018-09-281-2/+2
| | | | | | | | | | Review D52594 will change the default in llvm for armv6k from the non-existent cpu arm1176jf-s to mpcore. The tests in arm-cortex-cpus.c need to be updated to account for this change. Differential Revision: https://reviews.llvm.org/D52595 llvm-svn: 343304
* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-261-0/+20
| | | | | | | | | | | This patch allows targetting Armv8.5-A from Clang. Most of the implementation is in TargetParser, so this is mostly just adding tests. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52491 llvm-svn: 343111
* [ARM][AArch64] Add feature +fp16fmlSjoerd Meijer2018-09-241-10/+98
| | | | | | | | | | | | | | | | | | | | | Armv8.4-A adds a few FP16 instructions that can optionally be implemented in CPUs of Armv8.2-A and above. This patch adds a feature to clang to permit selection of these instructions. This interacts with the +fp16 option as follows: Prior to Armv8.4-A: *) +fp16fml implies +fp16 *) +nofp16 implies +nofp16fml From Armv8.4-A: *) The above conditions apply, additionally: +fp16 implies +fp16fml Patch by Bernard Ogden. Differential Revision: https://reviews.llvm.org/D50229 llvm-svn: 342862
* [AArch64][ARM] Add Armv8.4-A testsSjoerd Meijer2018-08-011-0/+49
| | | | | | | | | This adds tests for Armv8.4-A, and also some v8.2 and v8.3 tests that were missing. Differential Revision: https://reviews.llvm.org/D50068 llvm-svn: 338525
* [PATCH 2/2] [test] Add support for Samsung Exynos M4 (NFC)Evandro Menezes2018-06-061-12/+24
| | | | | | Add test cases for Exynos M4. llvm-svn: 334116
* [ARM] disable FPU features when using soft floating point.Keith Walker2018-02-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | To be compatible with GCC if soft floating point is in effect any FPU specified is effectively ignored, eg, -mfloat-abi=soft -fpu=neon If any floating point features which require FPU hardware are enabled they must be disable. There was some support for doing this for NEON, but it did not handle VFP, nor did it prevent the backend from emitting the build attribute Tag_FP_arch describing the generated code as using the floating point hardware if a FPU was specified (even though soft float does not use the FPU). Disabling the hardware floating point features for targets which are compiling for soft float has meant that some tests which were incorrectly checking for hardware support also needed to be updated. In such cases, where appropriate the tests have been updated to check compiling for soft float and a non-soft float variant (usually softfp). This was usually because the target specified in the test defaulted to soft float. Differential Revision: https://reviews.llvm.org/D42569 llvm-svn: 325492
* Revert [ARM] disable FPU features when using soft floating point.Keith Walker2017-11-301-3/+3
| | | | | | | This reverts r319420 It is failing the test Driver/arm-mfpu.c so reverting while I investigate the failure. llvm-svn: 319425
* [ARM] disable FPU features when using soft floating point.Keith Walker2017-11-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | To be compatible with GCC if soft floating point is in effect any FPU specified is effectively ignored, eg, -mfloat-abi=soft -fpu=neon If any floating point features which require FPU hardware are enabled they must be disable. There was some support for doing this for NEON, but it did not handle VFP, nor did it prevent the backend from emitting the build attribute Tag_FP_arch describing the generated code as using the floating point hardware if a FPU was specified (even though soft float does not use the FPU). Disabling the hardware floating point features for targets which are compiling for soft float has meant that some tests which were incorrectly checking for hardware support also needed to be updated. In such cases, where appropriate the tests have been updated to check compiling for soft float and a non-soft float variant (usually softfp). This was usually because the target specified in the test defaulted to soft float. Differential Revision: https://reviews.llvm.org/D40256 llvm-svn: 319420
* [ARM][AArch64] Cortex-A75 and Cortex-A55 testsSam Parker2017-08-211-0/+33
| | | | | | | | | | | | | | | | | | Add frontend tests for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36731 llvm-svn: 311319
* Adapt tests after making mcpu=generic the default for armv7-a and armv8-a.Kristof Beyls2017-06-011-6/+6
| | | | llvm-svn: 304391
* [ARM] Add regression tests for Cortex-M23 and Cortex-M33Sanne Wouda2017-02-201-0/+6
| | | | | | | | | | | | Reviewers: rengolin, t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30100 llvm-svn: 295647
* Add support for Samsung Exynos M3 (NFC)Evandro Menezes2016-12-131-0/+8
| | | | llvm-svn: 289614
* [ARM] Fix - missing target-cpu in testJaved Absar2016-10-121-1/+1
| | | | | | | | Fixes an incomplete test, wherein the target-cpu name (cortex-r52) was missing. Differential Revision: http://reviews.llvm.org/D25474 llvm-svn: 284009
* [ARM]: Add Cortex-R52 targetJaved Absar2016-10-071-0/+24
| | | | | | | This patch adds Cortex-R52, the new ARM real-time processor. Cortex-R52 implements the ARMv8-R architecture. llvm-svn: 283543
* [Driver] Report invalid -mtune/-mcpu parameters when -arch=arm64Vedant Kumar2016-09-081-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D23643 llvm-svn: 280998
* [AArch64] Add support for Samsung Exynos M2 (NFC).Evandro Menezes2016-08-011-0/+8
| | | | llvm-svn: 277365
* This adds target support and tests for Cortex-A73Sjoerd Meijer2016-06-021-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D20864 llvm-svn: 271507
* [ARM] Clang tests for ARM Cortex-A32 supportRenato Golin2016-03-211-0/+8
| | | | | | Patch by Sam Parker. llvm-svn: 263957
* Add more ARM Cortex-R8 regression tests to Clang.Pablo Barrio2016-03-161-0/+5
| | | | | | | | | | | | | | Summary: This patch adds Clang tests for Cortex-R8 related to FP capabilities and hardware integer divide. Reviewers: rengolin, bsmith Subscribers: aemerson, cfe-commits, rengolin Differential Revision: http://reviews.llvm.org/D18193 llvm-svn: 263632
* Add tests for ARM Cortex-R8Alexandros Lamprineas2016-03-111-0/+3
| | | | | | | | | | | Add command-line tests for ARM Cortex-R8 checking that the driver calls clang -cc1 with the correct little-endian/big-endian, and ARM/Thumb triple. Patch by Pablo Barrio <pablo.barrio@arm.com> Differential Revision: http://reviews.llvm.org/D18052 llvm-svn: 263245
* [ARM] Add Clang targeting for ARMv8-M Baseline/MainlineBradley Smith2016-03-031-0/+18
| | | | llvm-svn: 262619
* [ARM] Add command-line options for ARMv8.2-AOliver Stannard2016-02-111-4/+47
| | | | | | | | | | | | | | | | | This allows ARMv8.2-A to be targeted either by using "armv8.2a" in the triple, or by using -march=armv8.2-a (or the alias -march=armv8.2a). The FP16 extension can be enabled with the "+fp16" suffix to the -march or -mcpu option. This is consistent with the AArch64 option, rather than the usual ARM option of -mfpu. We have agreed with the team which will be upstreaming this to GCC that we want to use this new option format for new architecture extensions for both ARM and AArch64. Most of the work for this was done by the TargetParser patch in llvm. Differential Revision: http://reviews.llvm.org/D15040 llvm-svn: 260533
* [AArch64] Teaches clang about Samsung Exynos-M1MinSeong Kim2016-01-051-0/+8
| | | | | | | | Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15664 llvm-svn: 256829
* Teaches clang about Cortex-A35.Christof Douma2015-12-021-0/+8
| | | | | | | | Adds support for the new Cortex-A35 ARMv8-A core. Differential Revision: http://reviews.llvm.org/D15142 llvm-svn: 254505
* Handle ARMv6-J as an alias, instead of fake architectureArtyom Skrobov2015-11-201-2/+2
| | | | | | | | | | | | Summary: Clang-side update, corresponding to D14755 Reviewers: rengolin, bogden, compnerd Subscribers: aemerson, rengolin, cfe-commits Differential Revision: http://reviews.llvm.org/D14756 llvm-svn: 253677
* Handle ARMv6KZ namingArtyom Skrobov2015-11-161-4/+6
| | | | | | | | | | | | Summary: Update for clang tests for D14568 Reviewers: rengolin, joerg, bogden Subscribers: aemerson, rengolin, cfe-commits Differential Revision: http://reviews.llvm.org/D14570 llvm-svn: 253207
* [ARM] Fix crash "-target arm -mcpu=generic", without "-march="Vladimir Sukharev2015-09-231-0/+12
| | | | | | | | | | | | | | | | An assertion hit has been fixed for cmdlines like $ clang --target=arm-linux-gnueabi -mcpu=generic hello.c Related to: http://reviews.llvm.org/rL245445 Reviewers: rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D13013 llvm-svn: 248370
* [ARM] Proper generic cpus handlingVladimir Sukharev2015-08-191-0/+19
| | | | | | | | | | | | | | "generic" cpu was wrongly handled as exact real CPU name of ARMv8.1A architecture. This has been fixed, now it is abstract name, suitable for any arch. Reviewers: rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D11640 llvm-svn: 245445
* Allow case-insensitive values for -march for ARM in line with GCC.Gabor Ballabas2015-06-111-0/+9
| | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -march option for ARM. llvm-svn: 239527
* Allow case-insensitive values for -mcpu for ARMGabor Ballabas2015-06-041-0/+10
| | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -mcpu option. llvm-svn: 239059
* [ARM] Adjust -march checkingJohn Brawn2015-05-291-0/+4
| | | | | | | | | | getCanonicalArchName can return an empty string for an architecture that is well-formed but meaningless. Use parseArch to determine if it's actually valid or not. Differential Revision: http://reviews.llvm.org/D10120 llvm-svn: 238553
* [ARM] Be less specific about the error message expected.Ranjeet Singh2015-05-281-3/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D10087 llvm-svn: 238436
* Test commit.Ranjeet Singh2015-05-261-1/+1
| | | | llvm-svn: 238220
* [ARM] Restructure cpu handling in the driver to mostly use the tripleJohn Brawn2015-05-211-0/+4
| | | | | | | | | | | | | | | | | | Using the target cpu to determine some behaviour is sprinkled in several places in the driver, but in almost all the information that is needed can be found in the triple. Restructure things so that the triple is used, and the cpu is only used if the exact cpu name is needed. Also add a check that the -mcpu argument is valid, and correct the -march argument checking so that it handles -march=native correctly. I would have liked to move these checks into the computation of the triple, but the triple is calculated several times in several places and that would lead to multiple error messages for the same thing. Differential Revision: http://reviews.llvm.org/D9879 llvm-svn: 237894
* [ARM] Add v8.1a architectureVladimir Sukharev2015-05-141-0/+33
| | | | | | | | | | | | | | Add support for ARMv8.1a architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy, rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8799 llvm-svn: 237349
* Revert "Allow case-insensitive values for -mcpu for ARM and AArch64"Renato Golin2015-05-081-10/+0
| | | | | | | This reverts commit r236859, as it broke multiple builds. I'll investigate and reapply when safe. llvm-svn: 236869
* Allow case-insensitive values for -mcpu for ARM and AArch64Renato Golin2015-05-081-0/+10
| | | | | | | | | GCC allows case-insensitive values for -mcpu, -march and -mtune options. This patch implements the same behaviour for the -mcpu option. Patch by Gabor Ballabas. llvm-svn: 236859
* [ARM] Give an error on invalid -march valuesJohn Brawn2015-05-081-3/+3
| | | | | | | | | | llvm::Triple::getARMCPUForArch now returns nullptr for invalid -march values, instead of silently translating it to arm7tdmi. Use this to give an error message, which is consistent with how gcc behaves. Differential Revision: http://reviews.llvm.org/D9602 llvm-svn: 236846
* [ARM] add support for Cortex-R4/R4FJaved Absar2015-04-091-0/+8
| | | | | | | | Adds ARM Cortex-R4 and R4F support and tests in Clang. Though Cortex-R4 support was present, the support for hwdiv in thumb-mode was not defined or tested properly. This has also been added. llvm-svn: 234488
* [ARM] Add support for ARMV6K subtarget (Clang)Renato Golin2015-03-171-3/+26
| | | | | | | | | | | | | | | | | | | | | ARMv6K is another layer between ARMV6 and ARMV6T2. This is the Clang side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232469
* [ARM] Add missing M/R class CPUsBradley Smith2015-02-181-0/+13
| | | | | | | | | | | | Add some of the missing M and R class Cortex CPUs, namely: Cortex-M0+ (called Cortex-M0plus for GCC compatibility) Cortex-M1 SC000 SC300 Cortex-R5 llvm-svn: 229661
* [ARM] Add tests for armv6s[-]m being an alias to armv6[-]mBradley Smith2015-02-101-0/+2
| | | | llvm-svn: 228697
* Teaches the Clang driver to accept Cortex-A72Renato Golin2015-02-041-0/+8
| | | | | | | | | A previous commit added Cortex-A72 to LLVM, this teaches Clang to accept it as well. Patch by Ranjeet Singh. llvm-svn: 228141
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