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* Fix the problem that the range check for scalar narrow shift is too wide.Hao Liu2013-11-291-36/+36
| | | | | | E.g. the immediate value of vshrns_n_s16 is [1,16], which should be [1,8]. llvm-svn: 195942
* Add missing intrinsic function vbsl_f64 for AArch64 NEON.Jiangning Liu2013-11-291-0/+6
| | | | llvm-svn: 195940
* Add missing intrinsic function vcombine_f64 for AArch64 NEON.Jiangning Liu2013-11-291-0/+91
| | | | llvm-svn: 195937
* Fix the AArch64 NEON bug exposed by checking constant integer argument range ↵Jiangning Liu2013-11-271-192/+924
| | | | | | of ACLE intrinsics. llvm-svn: 195844
* [AArch64] Add support for NEON scalar floating-point absolute difference.Chad Rosier2013-11-271-0/+12
| | | | llvm-svn: 195804
* [AArch64] Add support for NEON scalar floating-point to integer convertChad Rosier2013-11-261-0/+133
| | | | | | instructions. llvm-svn: 195789
* Debug Info: add a "Debug Info Version" module flag to output the current debugManman Ren2013-11-221-0/+8
| | | | | | | | info version number. Will error out when modules have different version numbers. llvm-svn: 195495
* Revert r193994 and part of r193995Justin Bogner2013-11-221-8/+0
| | | | | | | | | | | | | Not long ago I made the CodeGen of for loops simplify the condition at -O0 in the same way we do for if and conditionals. Unfortunately this ties how loops and simple conditions work together too tightly, which makes features such as instrumentation based PGO awkward. Ultimately, we should find a more general way to simplify the logic in a given condition, but for now we'll just avoid using EmitBranchOnBool for loops, like we already do for while and do loops. llvm-svn: 195438
* Deleting three tests that are redundant with ↵Artyom Skrobov2013-11-223-15/+0
| | | | | | test/Preprocessor/arm-target-features.c and test/Driver/arm-cortex-cpus.c llvm-svn: 195430
* For AArch64, intrinsic vget_low_xxx can be optimized away.Jiangning Liu2013-11-221-42/+42
| | | | llvm-svn: 195409
* Implemented Neon scalar vdup_lane intrinsics.Ana Pazos2013-11-211-0/+173
| | | | | | Fixed scalar dup alias and added test case. llvm-svn: 195329
* Implemented Neon scalar by element intrinsics.Ana Pazos2013-11-211-11/+135
| | | | | | | Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane, vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics. llvm-svn: 195326
* [NVPTX] Update ABI handlingJustin Holewinski2013-11-201-0/+17
| | | | | | For PTX, we want the target to handle struct returns directly. llvm-svn: 195268
* Add a mangler entry point for TBAA rather than using RTTI directlyReid Kleckner2013-11-191-0/+22
| | | | | | | | | | | | | | | | | | | | Summary: RTTI is not yet implemented for the Microsoft C++ ABI and isn't expected soon. We could easily add the mangling, but the error is what prevents us from silently miscompiling code that expects RTTI. Instead, add a new mangleTypeName entry point that simply forwards to mangleName or mangleType to produce a string that isn't part of the ABI. Itanium can continue to use RTTI names to avoid unecessary test breakage. This also seems like the right design. The fact that TBAA names happen to be RTTI names is now an implementation detail of the mangler, rather than part of TBAA. Differential Revision: http://llvm-reviews.chandlerc.com/D2153 llvm-svn: 195168
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-0/+2047
| | | | llvm-svn: 195079
* Implement AArch64 SISD intrinsics for vget_high and vget_low.Jiangning Liu2013-11-191-0/+176
| | | | llvm-svn: 195073
* Add predicate for AArch64 crypto instructions.Jiangning Liu2013-11-191-1/+4
| | | | llvm-svn: 195069
* Implement the newly added AArch64 ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-181-0/+1120
| | | | | | The functions are like: vst1_s8_x2 ... llvm-svn: 194991
* Implement vreinterpret ACLE functions in Clang.Hao Liu2013-11-171-0/+2184
| | | | llvm-svn: 194954
* Implemented aarch64 Neon scalar vmulx_lane intrinsicsAna Pazos2013-11-152-0/+146
| | | | | | | | | | | | | | Implemented aarch64 Neon scalar vfma_lane intrinsics Implemented aarch64 Neon scalar vfms_lane intrinsics Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. Implemented legacy vfma_lane_f64, vfms_lane_f64, vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. llvm-svn: 194889
* These ACLE tests no longer need to cast the return value.Chad Rosier2013-11-151-8/+8
| | | | llvm-svn: 194854
* [AArch64] Add support for legacy AArch32 NEON scalar shift right by immediateChad Rosier2013-11-141-0/+24
| | | | | | and accumulate instructions. llvm-svn: 194732
* Remove a test failure.Kevin Qin2013-11-141-4/+0
| | | | llvm-svn: 194678
* Add test case for AArch64 NEON poly64 intrinsic.Kevin Qin2013-11-141-0/+287
| | | | llvm-svn: 194674
* Add test cases for AArch64 NEON instruction set misc.Kevin Qin2013-11-141-0/+1951
| | | | llvm-svn: 194672
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-141-0/+463
| | | | llvm-svn: 194649
* -fms-extensions: Recognize _alloca as an alias for the alloca builtinReid Kleckner2013-11-131-0/+9
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D1989 llvm-svn: 194617
* Only provide MS builtins when -fms-extensions is onReid Kleckner2013-11-131-1/+1
| | | | | | | | | | | We already have builtins that are only available in GNU mode, so this mirrors that. Reviewers: rsmith Differential Revision: http://llvm-reviews.chandlerc.com/D2128 llvm-svn: 194615
* [AArch64] Tests for legacy AArch32 NEON scalar shift by immediate instructions.Chad Rosier2013-11-131-0/+77
| | | | | | | A number of non-overloaded intrinsics have been replaced by thier overloaded counterparts. llvm-svn: 194599
* add intrinsics: __builtin_arm_{dmb,dsb} for ARMWeiming Zhao2013-11-121-1/+5
| | | | llvm-svn: 194513
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-122-0/+41
| | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
* [mips] Added fpu register tests to tests/CodeGen/mips-clobber-reg.cDaniel Sanders2013-11-121-0/+34
| | | | llvm-svn: 194474
* [mips] Small fixes to test/CodeGen/mips-clobber-reg.cDaniel Sanders2013-11-121-68/+70
| | | | | | | | Fixed the following: - Whitespace at end of most lines - $11 test actually testing $10 llvm-svn: 194473
* XCore target requires preferred alignment.Robert Lytton2013-11-121-3/+10
| | | | | | | | The xcore llvm backend does not handle 8 byte alignment viz: "%BadAlignment = alloca i64, align 8" So getPreferredTypeAlign() must never overalign. llvm-svn: 194462
* [mips] Partially revert r193640. Stack alignment should not be determined byAkira Hatanaka2013-11-112-5/+2
| | | | | | the floating point register mode. llvm-svn: 194426
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-111-8/+8
| | | | | | source operands, a vector, an element to insert, and a shift amount. llvm-svn: 194407
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-111-8/+32
| | | | | | instructions. llvm-svn: 194395
* ubsan: Only emit constants for filenames and type descriptors once.Will Dietz2013-11-081-2/+1
| | | | | | | | Produces neater IR in significantly less time. (~18% faster -O0 compile time for sqlite3 with -fsanitize=undefined) llvm-svn: 194231
* Implement AArch64 Neon instruction set Perm.Jiangning Liu2013-11-061-0/+1093
| | | | llvm-svn: 194124
* Implement AArch64 Neon instruction set Bitwise Extract.Jiangning Liu2013-11-061-0/+148
| | | | llvm-svn: 194119
* Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.Jiangning Liu2013-11-051-0/+91
| | | | llvm-svn: 194086
* Implemented aarch64 neon intrinsic vcopy_lane with float type.Kevin Qin2013-11-051-4/+226
| | | | llvm-svn: 194042
* CodeGen: Test that simple expressions are simplified at -O0Justin Bogner2013-11-041-0/+22
| | | | llvm-svn: 193995
* OS X 10.9+ and iOS 7+ support load/store of big atomic objects.Bob Wilson2013-11-021-0/+323
| | | | | | | | rdar://13973577 Patch by Fariborz Jahanian. llvm-svn: 193935
* [AArch64] Add support for NEON scalar fixed-point convert to floating-point ↵Chad Rosier2013-10-311-0/+24
| | | | | | instructions. llvm-svn: 193817
* [AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier2013-10-311-0/+263
| | | | llvm-svn: 193791
* [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related testsDaniel Sanders2013-10-301-8/+8
| | | | llvm-svn: 193695
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-301-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
* [AArch64] Add support for NEON scalar floating-point compare instructions.Chad Rosier2013-10-301-0/+169
| | | | llvm-svn: 193692
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-301-8/+8
| | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
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