Implemented aarch64 Neon scalar vmulx_lane intrinsics

Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.

llvm-svn: 194889

2 files changed, 146 insertions, 0 deletions

diff --git a/clang/test/CodeGen/aarch64-neon-2velem.c b/clang/test/CodeGen/aarch64-neon-2velem.c
index f34e11a3ce0..2a1eae4f16f 100644
--- a/clang/test/CodeGen/aarch64-neon-2velem.c
+++ b/clang/test/CodeGen/aarch64-neon-2velem.c
@@ -722,6 +722,14 @@ float32x2_t test_vmul_lane_f32(float32x2_t a, float32x2_t v) {
   // CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
 }
 
+
+float64x1_t test_vmul_lane_f64(float64x1_t a, float64x1_t v) {
+  // CHECK: test_vmul_lane_f64
+  return vmul_lane_f64(a, v, 0);
+  // CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+
 float32x4_t test_vmulq_lane_f32(float32x4_t a, float32x2_t v) {
   // CHECK: test_vmulq_lane_f32
   return vmulq_lane_f32(a, v, 1);
@@ -740,6 +748,13 @@ float32x2_t test_vmul_laneq_f32(float32x2_t a, float32x4_t v) {
   // CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
 }
 
+float64x1_t test_vmul_laneq_f64_0(float64x1_t a, float64x2_t v) {
+  // CHECK: test_vmul_laneq_f64_0
+  return vmul_laneq_f64(a, v, 0);
+  // CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+
 float32x4_t test_vmulq_laneq_f32(float32x4_t a, float32x4_t v) {
   // CHECK: test_vmulq_laneq_f32
   return vmulq_laneq_f32(a, v, 1);
diff --git a/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c b/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
new file mode 100644
index 00000000000..33cd48710c0
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
@@ -0,0 +1,131 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
+// RUN:   -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
+
+// Test new aarch64 intrinsics and types
+
+#include <arm_neon.h>
+
+
+float32_t test_vmuls_lane_f32(float32_t a, float32x2_t b) {
+  // CHECK: test_vmuls_lane_f32
+  return vmuls_lane_f32(a, b, 1);
+  // CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
+}
+
+float64_t test_vmuld_lane_f64(float64_t a, float64x1_t b) {
+  // CHECK: test_vmuld_lane_f64
+  return vmuld_lane_f64(a, b, 0);
+  // CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+float32_t test_vmuls_laneq_f32(float32_t a, float32x4_t b) {
+  // CHECK: test_vmuls_laneq_f32
+  return vmuls_laneq_f32(a, b, 3);
+  // CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
+}
+
+float64_t test_vmuld_laneq_f64(float64_t a, float64x2_t b) {
+  // CHECK: test_vmuld_laneq_f64
+  return vmuld_laneq_f64(a, b, 1);
+  // CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+}
+
+float64x1_t test_vmul_n_f64(float64x1_t a, float64_t b) {
+  // CHECK: test_vmul_n_f64
+  return vmul_n_f64(a, b);
+  // CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+float32_t test_vmulxs_lane_f32(float32_t a, float32x2_t b) {
+// CHECK: test_vmulxs_lane_f32
+  return vmulxs_lane_f32(a, b, 1);
+// CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
+}
+
+float32_t test_vmulxs_laneq_f32(float32_t a, float32x4_t b) {
+// CHECK: test_vmulxs_laneq_f32
+  return vmulxs_laneq_f32(a, b, 3);
+// CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
+}
+
+float64_t test_vmulxd_lane_f64(float64_t a, float64x1_t b) {
+// CHECK: test_vmulxd_lane_f64
+  return vmulxd_lane_f64(a, b, 0);
+// CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+float64_t test_vmulxd_laneq_f64(float64_t a, float64x2_t b) {
+// CHECK: test_vmulxd_laneq_f64
+  return vmulxd_laneq_f64(a, b, 1);
+// CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+}
+
+// CHECK_AARCH64: test_vmulx_lane_f64
+float64x1_t test_vmulx_lane_f64(float64x1_t a, float64x1_t b) {
+  return vmulx_lane_f64(a, b, 0);
+  // CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+
+// CHECK_AARCH64: test_vmulx_laneq_f64_0
+float64x1_t test_vmulx_laneq_f64_0(float64x1_t a, float64x2_t b) {
+  return vmulx_laneq_f64(a, b, 0);
+  // CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+// CHECK_AARCH64: test_vmulx_laneq_f64_1
+float64x1_t test_vmulx_laneq_f64_1(float64x1_t a, float64x2_t b) {
+  return vmulx_laneq_f64(a, b, 1);
+  // CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+}
+
+
+// CHECK_AARCH64: test_vfmas_lane_f32
+float32_t test_vfmas_lane_f32(float32_t a, float32_t b, float32x2_t c) {
+  return vfmas_lane_f32(a, b, c, 1);
+  // CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
+}
+
+// CHECK_AARCH64: test_vfmad_lane_f64
+float64_t test_vfmad_lane_f64(float64_t a, float64_t b, float64x1_t c) {
+  return vfmad_lane_f64(a, b, c, 0);
+  // CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+// CHECK_AARCH64: test_vfmad_laneq_f64
+float64_t test_vfmad_laneq_f64(float64_t a, float64_t b, float64x2_t c) {
+  return vfmad_laneq_f64(a, b, c, 1);
+  // CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+}
+
+// CHECK_AARCH64: test_vfmss_lane_f32
+float32_t test_vfmss_lane_f32(float32_t a, float32_t b, float32x2_t c) {
+  return vfmss_lane_f32(a, b, c, 1);
+  // CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
+}
+
+// CHECK_AARCH64: test_vfma_lane_f64
+float64x1_t test_vfma_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v) {
+  return vfma_lane_f64(a, b, v, 0);
+  // CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+// CHECK_AARCH64: test_vfms_lane_f64
+float64x1_t test_vfms_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v) {
+  return vfms_lane_f64(a, b, v, 0);
+  // CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+// CHECK_AARCH64: test_vfma_laneq_f64
+float64x1_t test_vfma_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v) {
+  return vfma_laneq_f64(a, b, v, 0);
+  // CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+
+// CHECK_AARCH64: test_vfms_laneq_f64
+float64x1_t test_vfms_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v) {
+  return vfms_laneq_f64(a, b, v, 0);
+  // CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
+}
+