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* Fix this test to handle NDEBUG builds which don't have a name for theChandler Carruth2016-06-111-4/+4
| | | | | | basic block. llvm-svn: 272456
* [AVX512] Implement 512-bit and masked shufflelo and shufflehi intrinsics ↵Craig Topper2016-06-112-6/+65
| | | | | | directly with __builtin_shufflevector and __builtin_ia32_select. Also improve the formatting of the AVX2 version. llvm-svn: 272452
* [AVX512] Add _mm512_bsrli_epi128 and _mm512_bslli_epi128 intrinsics.Craig Topper2016-06-111-0/+11
| | | | llvm-svn: 272451
* RenderScript support in the FrontendPirama Arumuga Nainar2016-06-091-0/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Create a new Frontend LangOpt to specify the renderscript language. It is enabled by the "-x renderscript" option from the driver. Add a "kernel" function attribute only for RenderScript (an "ignored attribute" warning is generated otherwise). Make the NativeHalfType and NativeHalfArgsAndReturns LangOpts be implied by the RenderScript LangOpt. Reviewers: rsmith Subscribers: cfe-commits, srhines Differential Revision: http://reviews.llvm.org/D21198 llvm-svn: 272342
* [X86] Handle AVX2 pslldqi and psrldqi intrinsics shufflevector creation ↵Craig Topper2016-06-091-4/+4
| | | | | | directly in the header file instead of in CGBuiltin.cpp. Simplify the sse2 equivalents as well. llvm-svn: 272246
* Specify target in lifetime-asan test.Vitaly Buka2016-06-081-3/+2
| | | | | | | | | | | | Summary: Some target platforms -fsanitize=address. Reviewers: pcc, eugenis Subscribers: cfe-commits, christof, chapuni, kubabrecka Differential Revision: http://reviews.llvm.org/D21117 llvm-svn: 272185
* [Sparc] Complex return value ABI compliance.Chris Dewhurst2016-06-081-0/+19
| | | | | | | | | | | | According to the Sparc V8 ABI, complex numbers should be passed and returned as pairs of registers: https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2734.html This fix ensures this is the case. Without this, complex numbers are returned as a struct of two floats, which breaks the ABI rules. Differential Review: http://reviews.llvm.org/D20955 llvm-svn: 272148
* [AVX512] Emit select instruction instead of using x86 specific instrinsics.Igor Breger2016-06-084-50/+50
| | | | | | | | This will allow us to remove the x86 instrinics from the backend. Differential Revision: http://reviews.llvm.org/D21060 llvm-svn: 272141
* [Clang][AVX512][BUILTIN]Adding intrinsics for range_round_{sd|ss}Michael Zuckerman2016-06-081-0/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D21002 llvm-svn: 272123
* [clang][AVX512][Intrinsics] Adding intrinsics reduce_[round]_{ss|sd} to clangMichael Zuckerman2016-06-071-0/+72
| | | | | | Differential Revision: http://reviews.llvm.org/D21014 llvm-svn: 272012
* [AVX512] Convert masked palignr builtins directly to native IR similar to ↵Craig Topper2016-06-062-7/+13
| | | | | | the other palignr builtins, but with a select to handle masking. llvm-svn: 271873
* [Clang][AVX512]Adding set4 intrinsicsMichael Zuckerman2016-06-051-0/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D20866 llvm-svn: 271835
* [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and ↵Michael Zuckerman2016-06-051-0/+35
| | | | | | | | _mm512_setzero_epi32 Differential Revision: http://reviews.llvm.org/D20871 llvm-svn: 271832
* [AVX512] Remove 512-bit andnot tests from the avx512vl test file.Craig Topper2016-06-041-36/+0
| | | | llvm-svn: 271795
* Suppress clang/test/CodeGen/lifetime-asan.c for targeting mingw.NAKAMURA Takumi2016-06-021-0/+1
| | | | | | clang.EXE: error: unsupported option '-fsanitize=address' for target 'x86_64-w64-windows-gnu' llvm-svn: 271509
* This adds target support and tests for Cortex-A73Sjoerd Meijer2016-06-021-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D20864 llvm-svn: 271507
* [X86][AVX512] add intrinsics of Scalar FP to integerAsaf Badouh2016-06-021-0/+77
| | | | | | Differential Revision: http://reviews.llvm.org/D20861 llvm-svn: 271499
* [Clang][AVX512][INTRINSICS] adding round cvt and fix regular cvtps_phMichael Zuckerman2016-06-021-4/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D20870 llvm-svn: 271498
* [asan] Added -fsanitize-address-use-after-scope flagVitaly Buka2016-06-021-0/+21
| | | | | | | | | | | | | | | | Summary: Also emit lifetime markers for -fsanitize-address-use-after-scope. Asan uses life-time markers for use-after-scope check. PR27453 Reviewers: kcc, eugenis, aizatsky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20759 llvm-svn: 271451
* [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) ↵Simon Pilgrim2016-06-013-6/+3
| | | | | | | | | | | | f32/f64 to i32 with generic IR (clang) The 'cvtt' truncation (round to zero) conversions can be safely represented as generic __builtin_convertvector (fptosi) calls instead of x86 intrinsics. We already do this (implicitly) for the scalar equivalents. Note: I looked at updating _mm_cvttpd_epi32 as well but this still requires a lot more backend work to correctly lower (both for debug and optimized builds). Differential Revision: http://reviews.llvm.org/D20859 llvm-svn: 271436
* [Clang][Intrinsics][avx512] Continue Adding round cvt to clangMichael Zuckerman2016-06-011-22/+86
| | | | | | | And remove trailing spaces in intrinsic f test Differential Revision: http://reviews.llvm.org/D20810 llvm-svn: 271398
* Adding front-end support to several intrinsics (bit scanning, conversion and ↵Michael Zuckerman2016-06-013-0/+56
| | | | | | | | | | | | | | | | | | | state reading intrinsics) Adding LLVM front-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse. Their functionality is as described in Intel intrinsics guide: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370 Furthermore, adding clang front-end support to these conversion intrinsics: _mm256_cvtsd_f64, _mm256_cvtsi256_si32 and _mm256_cvtss_f32. Finally, adding tests to all of the above, as well as to the state reading intrinsics _rdpmc and _rdtsc. Their functionality is also specified in the Intel intrinsics guide. Commit on behalf of Omer Paparo Bivas llvm-svn: 271387
* [Clang][Intrinsics][avx512] Adding round intrinsics fot max/min/sqrt ↵Michael Zuckerman2016-06-011-0/+126
| | | | | | | | instruction set to clang Differential Revision: http://reviews.llvm.org/D20812 llvm-svn: 271373
* [Clang][Intrinsics][avx512] Adding round roundscale to clangMichael Zuckerman2016-06-011-0/+42
| | | | | | Differential Revision: http://reviews.llvm.org/D20815 llvm-svn: 271368
* CodeGen: tweak CFString emission for COFF targetsSaleem Abdulrasool2016-06-011-0/+40
| | | | | | | | | The `isa' member was previously not given the correct DLL Storage. Ensure that we give the `isa' constant `__CFConstantStringClassReference' the correct DLL storage. Default to dllimport unless an explicit specification gives it a dllexport storage. llvm-svn: 271361
* AMDGPU: Update datalayout stringMatt Arsenault2016-05-311-2/+2
| | | | llvm-svn: 271297
* [ARM] Add load/store co-processor intrinsics.Ranjeet Singh2016-05-311-0/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D20563 llvm-svn: 271275
* [Clang][Intrinsics][avx512] Adding round cvt to clangMichael Zuckerman2016-05-311-0/+134
| | | | | | Differential Revision: http://reviews.llvm.org/D20790 llvm-svn: 271265
* [AVX512] Convert masked load builtins to generic masked load intrinsics ↵Craig Topper2016-05-314-59/+59
| | | | | | | | instead of the x86 specific ones. This will allow the x86 intrinsics to be removed from the backend. llvm-svn: 271253
* [AVX512] Emit generic masked store instrinsics instead of using x86 specific ↵Craig Topper2016-05-314-32/+35
| | | | | | | | intrinsics. This will allow us to remove the x86 instrinics from the backend. llvm-svn: 271246
* [X86] Ensure load/store tests unaligned pointers really are align 1Simon Pilgrim2016-05-303-16/+16
| | | | llvm-svn: 271227
* [X86][SSE] Added missing tests (merge failure)Simon Pilgrim2016-05-301-4/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D20617 llvm-svn: 271219
* [X86][SSE] _mm_store1_ps/_mm_store1_pd should require an aligned pointerSimon Pilgrim2016-05-301-3/+9
| | | | | | | | | | | | | | | | According to the gcc headers, intel intrinsics docs and msdn codegen the _mm_store1_pd (and its _mm_store_pd1 equivalent) should use an aligned pointer - the clang headers are the only implementation I can find that assume non-aligned stores (by storing with _mm_storeu_pd). Additionally, according to the intel intrinsics docs and msdn codegen the _mm_store1_ps (_mm_store_ps1) requires a similarly aligned pointer. This patch raises the alignment requirements to match the other implementations by calling _mm_store_ps/_mm_store_pd instead. I've also added the missing _mm_store_pd1 intrinsic (which maps to _mm_store1_pd like _mm_store_ps1 does to _mm_store1_ps). As a followup I'll update the llvm fast-isel tests to match this codegen. Differential Revision: http://reviews.llvm.org/D20617 llvm-svn: 271218
* [X86] Replace unaligned store builtins in SSE/AVX intrinsic files with code ↵Craig Topper2016-05-304-20/+22
| | | | | | | | that will compile to a native unaligned store. Remove the builtins since they are no longer used. Intrinsics will be removed from llvm in a future commit. llvm-svn: 271214
* test: add explicit targets for some testsSaleem Abdulrasool2016-05-302-2/+6
| | | | | | | These tests currently expect MachO section names and do not provide a target. Explicitly provide one. llvm-svn: 271212
* CodeGen: tweak CFConstantStrings for COFF and ELFSaleem Abdulrasool2016-05-301-0/+49
| | | | | | | | Adjust the constant CFString emission to emit into more appropriate sections on ELF and COFF targets. It would previously try to use MachO section names irrespective of the file format. llvm-svn: 271211
* [Clang][avx512][builtin] Adding missing intrinsics for cvtMichael Zuckerman2016-05-301-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D20618 llvm-svn: 271205
* Mark test as requiring x86-registered-target.Rafael Espindola2016-05-291-0/+1
| | | | llvm-svn: 271163
* Handle -Wa,--mrelax-relocations=[no|yes].Rafael Espindola2016-05-291-0/+9
| | | | llvm-svn: 271162
* CodeGen: support blocks on COFF targets in DLLsSaleem Abdulrasool2016-05-281-0/+76
| | | | | | | | | | | This extends the blocks support to support blocks with a dynamically linked blocks runtime. The previous code generation would work only for static builds of the blocks runtime. Mark the block "isa" pointers and functions as dllimport if no explicit declaration marked with __declspec(dllexport) is found. This additional check allows for the use of the functionality in the runtime library if desired. llvm-svn: 271138
* [AVX512] Add masked v16i32 and v8i64 unaligned store tests.Craig Topper2016-05-281-0/+12
| | | | llvm-svn: 271134
* [X86][SSE] Replace VPMOVSX and (V)PMOVZX integer extension intrinsics with ↵Simon Pilgrim2016-05-283-24/+30
| | | | | | | | | | | | | | generic IR (clang) The VPMOVSX and (V)PMOVZX sign/zero extension intrinsics can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics. This patch removes the clang builtins and their use in the sse2/avx headers - a companion patch will remove/auto-upgrade the llvm intrinsics. Note: We already did this for SSE41 PMOVSX sometime ago. Differential Revision: http://reviews.llvm.org/D20684 llvm-svn: 271106
* [CodeGen] Don't crash when sizeof(long) != 4 for some intrinsDavid Majnemer2016-05-271-0/+23
| | | | | | | | | | _InterlockedIncrement and _InterlockedDecrement have 'long' in their prototypes. We assumed 'long' was the same size as an i32 which is incorrect for other targets. This fixes PR27892. llvm-svn: 270953
* Adding missing _mm512_castsi512_si256 intrinsic. Michael Zuckerman2016-05-261-0/+7
| | | | llvm-svn: 270851
* [X86][F16C] Improved f16c intrinsics checks Simon Pilgrim2016-05-261-6/+20
| | | | | | Added checks for upper elements being zero'd in scalar conversions llvm-svn: 270836
* [X86][AVX2] Improved checks for float/double mask generation for non-masked ↵Simon Pilgrim2016-05-261-0/+8
| | | | | | gathers llvm-svn: 270833
* Fix instrinsics names: Michael Zuckerman2016-05-261-15/+12
| | | | | | | | | _mm128_cmp_ps_mask-->_mm_cmp_ps_mask _mm128_mask_cmp_ps_mask-->_mm_mask_cmp_ps_mask _mm128_cmp_pd_mask-->_mm_cmp_pd_mask _mm128_mask_cmp_pd_mask-->_mm_mask_cmp_pd_mask llvm-svn: 270830
* [Clang][AVX512][BUILTIN] Adding intrinsics for set1Michael Zuckerman2016-05-261-0/+30
| | | | | | Differential Revision: http://reviews.llvm.org/D20562 llvm-svn: 270825
* [X86][AVX2] Full set of AVX2 intrinsics testsSimon Pilgrim2016-05-251-600/+745
| | | | | | llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll will be synced to this llvm-svn: 270708
* [AVX512] Don't rely on value names. They're different in release builds.Benjamin Kramer2016-05-251-9/+9
| | | | llvm-svn: 270704
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