summaryrefslogtreecommitdiffstats
path: root/clang/test/CodeGen
diff options
context:
space:
mode:
authorMichael Zuckerman <Michael.zuckerman@intel.com>2016-06-01 12:21:00 +0000
committerMichael Zuckerman <Michael.zuckerman@intel.com>2016-06-01 12:21:00 +0000
commite54093fcc0a651df14040a61fc8efdd338389afa (patch)
tree91e412aea314b227db28d417c7d55dc58997786c /clang/test/CodeGen
parent6a894956fccdc5a951ee014eb130c68c94a2f377 (diff)
downloadbcm5719-llvm-e54093fcc0a651df14040a61fc8efdd338389afa.tar.gz
bcm5719-llvm-e54093fcc0a651df14040a61fc8efdd338389afa.zip
Adding front-end support to several intrinsics (bit scanning, conversion and state reading intrinsics)
Adding LLVM front-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse. Their functionality is as described in Intel intrinsics guide: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370 Furthermore, adding clang front-end support to these conversion intrinsics: _mm256_cvtsd_f64, _mm256_cvtsi256_si32 and _mm256_cvtss_f32. Finally, adding tests to all of the above, as well as to the state reading intrinsics _rdpmc and _rdtsc. Their functionality is also specified in the Intel intrinsics guide. Commit on behalf of Omer Paparo Bivas llvm-svn: 271387
Diffstat (limited to 'clang/test/CodeGen')
-rw-r--r--clang/test/CodeGen/avx-builtins.c21
-rw-r--r--clang/test/CodeGen/bitscan-builtins.c17
-rw-r--r--clang/test/CodeGen/rd-builtins.c18
3 files changed, 56 insertions, 0 deletions
diff --git a/clang/test/CodeGen/avx-builtins.c b/clang/test/CodeGen/avx-builtins.c
index e15e22a2ed6..c1b8cf2c919 100644
--- a/clang/test/CodeGen/avx-builtins.c
+++ b/clang/test/CodeGen/avx-builtins.c
@@ -1385,3 +1385,24 @@ void test_mm256_zeroupper() {
// CHECK: call void @llvm.x86.avx.vzeroupper()
return _mm256_zeroupper();
}
+
+double test_mm256_cvtsd_f64(__m256d __a)
+{
+ // CHECK-LABEL: @test_mm256_cvtsd_f64
+ // CHECK: extractelement <4 x double> %{{.*}}, i32 0
+ return _mm256_cvtsd_f64(__a);
+}
+
+int test_mm256_cvtsi256_si32(__m256i __a)
+{
+ // CHECK-LABEL: @test_mm256_cvtsi256_si32
+ // CHECK: extractelement <8 x i32> %{{.*}}, i32 0
+ return _mm256_cvtsi256_si32(__a);
+}
+
+float test_mm256_cvtss_f32(__m256 __a)
+{
+ // CHECK-LABEL: @test_mm256_cvtss_f32
+ // CHECK: extractelement <8 x float> %{{.*}}, i32 0
+ return _mm256_cvtss_f32(__a);
+}
diff --git a/clang/test/CodeGen/bitscan-builtins.c b/clang/test/CodeGen/bitscan-builtins.c
new file mode 100644
index 00000000000..85a75426342
--- /dev/null
+++ b/clang/test/CodeGen/bitscan-builtins.c
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s
+
+// Don't include mm_malloc.h, it's system specific.
+#define __MM_MALLOC_H
+#include <immintrin.h>
+
+int test_bit_scan_forward(int a) {
+ return _bit_scan_forward(a);
+// CHECK: @test_bit_scan_forward
+// CHECK: call i32 @llvm.x86.bit.scan.forward
+}
+
+int test_bit_scan_reverse(int a) {
+ return _bit_scan_reverse(a);
+// CHECK: @test_bit_scan_reverse
+// CHECK: call i32 @llvm.x86.bit.scan.reverse
+}
diff --git a/clang/test/CodeGen/rd-builtins.c b/clang/test/CodeGen/rd-builtins.c
new file mode 100644
index 00000000000..5cad9039094
--- /dev/null
+++ b/clang/test/CodeGen/rd-builtins.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s
+
+// Don't include mm_malloc.h, it's system specific.
+#define __MM_MALLOC_H
+
+#include <x86intrin.h>
+
+unsigned long long test_rdpmc(int a) {
+ return _rdpmc(a);
+// CHECK: @test_rdpmc
+// CHECK: call i64 @llvm.x86.rdpmc
+}
+
+int test_rdtsc() {
+ return _rdtsc();
+// CHECK: @test_rdtsc
+// CHECK: call i64 @llvm.x86.rdtsc
+}
OpenPOWER on IntegriCloud