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* [X86] Add guards to some of the x86 intrinsic tests to skip 64-bit mode only ↵Craig Topper2019-07-101-0/+4
| | | | | | | | | | intrinsics when compiled for 32-bit mode. All the command lines are for 64-bit mode, but sometimes I compile the tests in 32-bit mode to see what assembly we get and we need to skip these to do that. llvm-svn: 365668
* [X86] Update handling in CGBuiltin to be tolerant of out of range immediates.Craig Topper2018-06-211-7/+7
| | | | | | | | D48464 contains changes that will loosen some of the range checks in SemaChecking to a DefaultError warning that can be disabled. This patch adds explicit masking to avoid using the upper bits of immediates to gracefully handle the warning being disabled. llvm-svn: 335308
* [X86] Add builtins for vector element insert and extract for different 128 ↵Craig Topper2018-06-061-6/+6
| | | | | | | | | | | | | | and 256 bit vector types. Use them to implement the extract and insert intrinsics. Previously we were just using extended vector operations in the header file. This unfortunately allowed non-constant indices to be used with the intrinsics. This is incompatible with gcc, icc, and MSVC. It also introduces a different performance characteristic because non-constant index gets lowered to a vector store and an element sized load. By adding the builtins we can check for the index to be a constant and ensure its in range of the vector element count. User code still has the option to use extended vector operations themselves if they need non-constant indexing. llvm-svn: 334057
* [X86] NFC Include immintrin.h in CodeGen testsGabor Buella2018-05-241-1/+1
| | | | | | | Following r333110: "Move all Intel defined intrinsic includes into immintrin.h" llvm-svn: 333160
* [X86] Emit native IR for pmuldq/pmuludq builtins.Craig Topper2018-04-091-1/+5
| | | | | | | | I believe all the pieces are now in place in the backend to make this work correctly. We can either mask the input to 32 bits for pmuludg or shl/ashr for pmuldq and use a regular mul instruction. The backend should combine this to PMULUDQ/PMULDQ and then SimplifyDemandedBits will remove the and/shifts. Differential Revision: https://reviews.llvm.org/D45421 llvm-svn: 329605
* [X86][SSE] Update MOVNTDQA non-temporal loads to generic implementation (clang)Simon Pilgrim2017-04-141-1/+1
| | | | | | | | | | MOVNTDQA non-temporal aligned vector loads can be correctly represented using generic builtin loads, allowing us to remove the existing x86 intrinsics. LLVM companion patch: D31767. Differential Revision: https://reviews.llvm.org/D31766 llvm-svn: 300326
* [X86] Remove the mm_malloc.h include guard hack from the X86 builtins testsElad Cohen2016-09-281-4/+2
| | | | | | | | | | | | The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted environment since it expects stdlib.h to be available - which is not the case in these internal clang codegen tests). This patch removes this hack and instead passes -ffreestanding to clang cc1. Differential Revision: https://reviews.llvm.org/D24825 llvm-svn: 282581
* After PR28761 use -Wall with -Werror in builtins tests to identifyEric Christopher2016-08-041-2/+2
| | | | | | possible problems in headers. llvm-svn: 277696
* [X86] Uncomment the _mm_extract_ps test and add checks.Craig Topper2016-07-091-4/+5
| | | | llvm-svn: 274965
* [x86] generate IR for SSE integer min/max builtinsSanjay Patel2016-06-151-8/+16
| | | | | | | Sibling patch to r272806: http://reviews.llvm.org/rL272806 llvm-svn: 272807
* [X86][SSE] Replace VPMOVSX and (V)PMOVZX integer extension intrinsics with ↵Simon Pilgrim2016-05-281-6/+12
| | | | | | | | | | | | | | generic IR (clang) The VPMOVSX and (V)PMOVZX sign/zero extension intrinsics can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics. This patch removes the clang builtins and their use in the sse2/avx headers - a companion patch will remove/auto-upgrade the llvm intrinsics. Note: We already did this for SSE41 PMOVSX sometime ago. Differential Revision: http://reviews.llvm.org/D20684 llvm-svn: 271106
* [X86][SSE41] Sync with llvm/test/CodeGen/X86/sse41-intrinsics-fast-isel.llSimon Pilgrim2016-05-181-20/+20
| | | | llvm-svn: 269926
* Updated SSE41 builtin tests to more closely match the llvm fast-isel ↵Simon Pilgrim2016-03-011-40/+50
| | | | | | equivalent tests llvm-svn: 262418
* [X86] Stripped backend codegen testsSimon Pilgrim2015-12-031-90/+27
| | | | | | | | | | As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
* Canonicalize some of the x86 builtin tests and either remove or commentEric Christopher2015-10-141-4/+4
| | | | | | about optimization options. llvm-svn: 250271
* [Headers][X86] Fix stream_load (movntdqa) to accept const*.Ahmed Bougacha2015-10-021-1/+1
| | | | | | | | | | Per Intel intrinsics guide: - _mm256_stream_load_si256 takes `__m256i const *' - _mm_stream_load_si128 takes `__m128i *', for no good reason. Let's accept const* for both. llvm-svn: 249213
* Patch over a really horrible bug in our vector builtins that showed upChandler Carruth2015-10-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | recently when we started using direct conversion to model sign extension. The __v16qi type we use for SSE v16i8 vectors is defined in terms of 'char' which may or may not be signed! This causes us to generate pmovsx and pmovzx depending on the setting of -funsigned-char. This patch just forms an explicitly signed type and uses that to formulate the sign extension. While this gets the correct behavior (which we now verify with the enhanced test) this is just the tip of the ice berg. Now that I know what to look for, I have found errors of this sort *throughout* our vector code. Fortunately, this is the only specific place where I know of users actively having their code miscompiled by Clang due to this, so I'm keeping the fix for those users minimal and targeted. I'll be sending a proper email for discussion of how to fix these systematically, what the implications are, and just how widely broken this is... From what I can tell, we have never shipped a correct set of builtin headers for x86 when users rely on -funsigned-char. Oops. llvm-svn: 248980
* [X86][SSE] Replace 128-bit SSE41 PMOVSX intrinsics with native IRSimon Pilgrim2015-09-191-6/+6
| | | | | | | | | | 128-bit vector integer sign extensions correctly lower to the pmovsx instructions even for debug builds. This patch removes the builtins and reimplements the _mm_cvtepi*_epi* intrinsics __using builtin_shufflevector (to extract the bottom most subvector) and __builtin_convertvector (to actually perform the sign extension). Differential Revision: http://reviews.llvm.org/D12835 llvm-svn: 248092
* [X86]][SSE3] Added SSE41 IR + assembly codegen builtin testsSimon Pilgrim2015-09-061-0/+433
Transferred SSE41 instructions from sse-builtins.c llvm-svn: 246947
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