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* AArch64: add arm64_32 support to Clang.Tim Northover2019-11-121-1/+2
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* [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLEvhscampos2019-10-281-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Writing support for three ACLE functions: unsigned int __cls(uint32_t x) unsigned int __clsl(unsigned long x) unsigned int __clsll(uint64_t x) CLS stands for "Count number of leading sign bits". In AArch64, these two intrinsics can be translated into the 'cls' instruction directly. In AArch32, on the other hand, this functionality is achieved by implementing it in terms of clz (count number of leading zeros). Reviewers: compnerd Reviewed By: compnerd Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69250
* Allow prefetching from non-zero address spacesJF Bastien2019-07-251-4/+4
| | | | | | | | | | | | | | | Summary: This is useful for targets which have prefetch instructions for non-default address spaces. <rdar://problem/42662136> Subscribers: nemanjai, javed.absar, hiraditya, kbarton, jkorous, dexonsmith, cfe-commits, llvm-commits, RKSimon, hfinkel, t.p.northover, craig.topper, anemet Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65254 llvm-svn: 367032
* [AArch64] Implement __jcvt intrinsic from Armv8.3-AKyrylo Tkachov2019-07-161-0/+6
| | | | | | | | | | | | | | | | The jcvt intrinsic defined in ACLE [1] is available when ARM_FEATURE_JCVT is defined. This change introduces the AArch64 intrinsic, wires it up to the instruction and a new clang builtin function. The __ARM_FEATURE_JCVT macro is now defined when an Armv8.3-A or higher target is used. I've implemented the target detection logic in Clang so that this feature is enabled for architectures from armv8.3-a onwards (so -march=armv8.4-a also enables this, for example). make check-all didn't show any new failures. [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics Differential Revision: https://reviews.llvm.org/D64495 llvm-svn: 366197
* [AArch64] Update int64_t ACLE builtin argumentsSam Parker2019-01-291-4/+16
| | | | | | | | Re-applying r351740 with fixes (changing LL to W). Differential Revision: https://reviews.llvm.org/D56852 llvm-svn: 352463
* [AArch64] Make the test for rsr and rsr64 stricterPetr Hosek2019-01-251-2/+7
| | | | | | | | | | | | | | | ACLE specifies that return type for rsr and rsr64 is uint32_t and uint64_t respectively. D56852 change the return type of rsr64 from unsigned long to unsigned long long which at least on Linux doesn't match uint64_t, but the test isn't strict enough to detect that because compiler implicitly converts unsigned long long to uint64_t, but it breaks other uses such as printf with PRIx64 type specifier. This change makes the test stricter enforcing that the return type of rsr and rsr64 builtins is what is actually specified in ACLE. Differential Revision: https://reviews.llvm.org/D57210 llvm-svn: 352156
* Revert "[AArch64] Use LL for 64-bit intrinsic arguments"Petr Hosek2019-01-251-4/+2
| | | | | | | | | | This reverts commit r351740: this broke on platforms where unsigned long long isn't the same as uint64_t which is what ACLE specifies for the return value of rsr64. Differential Revision: https://reviews.llvm.org/D57209 llvm-svn: 352153
* [AArch64] Use LL for 64-bit intrinsic argumentsSam Parker2019-01-211-2/+4
| | | | | | | | | | The ACLE states that 64-bit crc32, wsr, rsr and rbit operands are uint64_t so we should have the clang builtin match this description - which is what we already do for AArch32. Differential Revision: https://reviews.llvm.org/D56852 llvm-svn: 351740
* IRGen: Add optnone attribute on function during O0Mehdi Amini2017-05-291-1/+1
| | | | | | | | | | | Amongst other, this will help LTO to correctly handle/honor files compiled with O0, helping debugging failures. It also seems in line with how we handle other options, like how -fnoinline adds the appropriate attribute as well. Differential Revision: https://reviews.llvm.org/D28404 llvm-svn: 304127
* [AArch64] Use generic bitreverse intrinsic, rather than AArch64 specific.Chad Rosier2017-01-101-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D28400 llvm-svn: 291574
* [Builtin] Make __builtin_thread_pointer target-independent.Marcin Koscielnicki2016-06-161-1/+1
| | | | | | | | This is now supported for ARM, AArch64, PowerPC, SystemZ, SPARC, Mips. Differential Revision: http://reviews.llvm.org/D19589 llvm-svn: 272893
* [AArch64] Fix D19098 fallout.Marcin Koscielnicki2016-04-191-1/+1
| | | | | | | | | | The intrinsic is now called llvm.thread.pointer, not llvm.aarch64.thread.pointer. Also, the code handling it in CGBuiltin.cpp is dead - it's already covered by GCCBuiltin. Remove it. Differential Revision: http://reviews.llvm.org/D19099 llvm-svn: 266817
* ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.Tim Northover2016-03-091-3/+3
| | | | | | | | | | | | | | | This is mostly a one-time autoconversion of tests that checked assembly after "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This should make them much more stable to changes in LLVM so they won't break on unrelated changes. "opt -mem2reg" is a compromise designed to increase the readability of tests that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is stable enough that no surpises will come along. Should address http://llvm.org/PR26815. llvm-svn: 263048
* [AArch64] Implement __builtin_thread_pointerAdhemerval Zanella2015-07-281-0/+5
| | | | | | | This path add the aarch64 __builtin_thread_pointer support. It will be lowered to llvm.aarch64.thread.pointer. llvm-svn: 243413
* [ARM] Replace hard coded metadata arguments in tests with a regex.Ranjeet Singh2015-06-171-7/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D10507 llvm-svn: 239932
* This patch implements clang support for the ACLE special register intrinsicsLuke Cheeseman2015-06-151-0/+36
| | | | | | | | | | | | | in section 10.1, __arm_{w,r}sr{,p,64}. This includes arm_acle.h definitions with builtins and codegen to support these, the intrinsics are implemented by generating read/write_register calls which get appropriately lowered in the backend based on the register string provided. SemaChecking is also implemented to fault invalid parameters. Differential Revision: http://reviews.llvm.org/D9697 llvm-svn: 239737
* AArch64: Prefetch intrinsicYi Kong2014-08-131-0/+14
| | | | llvm-svn: 215569
* Port memory barriers intrinsics to AArch64Yi Kong2014-07-171-0/+6
| | | | | | | | | | | | | Memory barrier __builtin_arm_[dmb, dsb, isb] intrinsics are required to implement their corresponding ACLE and MSVC intrinsics. This patch ports ARM dmb, dsb, isb intrinsic to AArch64. Requires LLVM r213247. Differential Revision: http://reviews.llvm.org/D4521 llvm-svn: 213250
* ARM: Implement __builtin_arm_nop intrinsicYi Kong2014-07-141-0/+1
| | | | | | | | | | | This patch implements __builtin_arm_nop intrinsic for AArch32 and AArch64, which generates hint 0x0, the alias of NOP instruction. This intrinsic is necessary to implement ACLE __nop intrinsic. Differential Revision: http://reviews.llvm.org/D4495 llvm-svn: 212947
* Add test cases for AArch64 hints codegenYi Kong2014-07-131-0/+8
| | | | llvm-svn: 212909
* AArch64: Fix silly think-o in tests.Jim Grosbach2014-06-161-4/+4
| | | | | | rdar://9283021 llvm-svn: 211064
* AArch64: Support for __builtin_arm_rbit() and __builtin_arm_rbit64().Jim Grosbach2014-06-161-0/+10
| | | | | | | | __builtin_arm_rbit() and __builtin_arm_rbit64(). rdar://9283021 llvm-svn: 211060
* ARM64: initial clang support commit.Tim Northover2014-03-291-0/+6
This adds Clang support for the ARM64 backend. There are definitely still some rough edges, so please bring up any issues you see with this patch. As with the LLVM commit though, we think it'll be more useful for merging with AArch64 from within the tree. llvm-svn: 205100
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