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* [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLEvhscampos2019-10-281-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Writing support for three ACLE functions: unsigned int __cls(uint32_t x) unsigned int __clsl(unsigned long x) unsigned int __clsll(uint64_t x) CLS stands for "Count number of leading sign bits". In AArch64, these two intrinsics can be translated into the 'cls' instruction directly. In AArch32, on the other hand, this functionality is achieved by implementing it in terms of clz (count number of leading zeros). Reviewers: compnerd Reviewed By: compnerd Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69250
* Allow prefetching from non-zero address spacesJF Bastien2019-07-251-4/+3
| | | | | | | | | | | | | | | Summary: This is useful for targets which have prefetch instructions for non-default address spaces. <rdar://problem/42662136> Subscribers: nemanjai, javed.absar, hiraditya, kbarton, jkorous, dexonsmith, cfe-commits, llvm-commits, RKSimon, hfinkel, t.p.northover, craig.topper, anemet Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65254 llvm-svn: 367032
* [ARM] Add tests for the vcvtr builtinsSjoerd Meijer2018-02-161-22/+38
| | | | | | | | | This adds Sema and Codegen tests for the vcvtr builtins (because they were missing). Differential Revision: https://reviews.llvm.org/D43372 llvm-svn: 325351
* IRGen: Add optnone attribute on function during O0Mehdi Amini2017-05-291-1/+1
| | | | | | | | | | | Amongst other, this will help LTO to correctly handle/honor files compiled with O0, helping debugging failures. It also seems in line with how we handle other options, like how -fnoinline adds the appropriate attribute as well. Differential Revision: https://reviews.llvm.org/D28404 llvm-svn: 304127
* [ARM] Use generic bitreverse intrinsic, rather than ARM specific rbit.Chad Rosier2017-01-101-1/+1
| | | | | | The backend already supports lowering this intrinsic to a rbit instruction. llvm-svn: 291582
* [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.Ranjeet Singh2016-06-171-8/+22
| | | | | | | | | | Reapplying patch in r272777 which was reverted because the llvm patch which added support for generating the mcrr/mcrr2 instructions from the intrinsic was causing an assertion failure. This has now been fixed in llvm. llvm-svn: 272983
* Reverting r272777 because one of the testsRanjeet Singh2016-06-151-22/+8
| | | | | | | added in the llvm patch is causing an assertion to fail. llvm-svn: 272790
* [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.Ranjeet Singh2016-06-151-8/+22
| | | | | | | | | | | | | | Patch adds intrinsics for mrrc/mrrc2. The intrinsics for mrrc/mrrc2 return a single uint64_t to represent two 32 bit values. The mcrr/mcrr2 intrinsic was changed to accept a single uint64_t instead of two 32 bit values as the input for consistency. Differential Revision: http://reviews.llvm.org/D21179 llvm-svn: 272777
* [ARM] Add load/store co-processor intrinsics.Ranjeet Singh2016-05-311-0/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D20563 llvm-svn: 271275
* [ARM] Fix cdp intrinsicRanjeet Singh2016-05-191-0/+14
| | | | | | | | | | | - Fixed cdp intrinsic to only accept compile time constant values previously you could pass in a variable to the builtin which would result in illegal llvm assembly output Differential Revision: http://reviews.llvm.org/D20394 llvm-svn: 270058
* ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.Tim Northover2016-03-091-13/+12
| | | | | | | | | | | | | | | This is mostly a one-time autoconversion of tests that checked assembly after "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This should make them much more stable to changes in LLVM so they won't break on unrelated changes. "opt -mem2reg" is a compromise designed to increase the readability of tests that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is stable enough that no surpises will come along. Should address http://llvm.org/PR26815. llvm-svn: 263048
* [ARM] Mark mcr/mrc builtin operands as required-immediate.Ahmed Bougacha2015-08-261-0/+38
| | | | | | An early error message is better than the "cannot select" alternative. llvm-svn: 246094
* This patch implements clang support for the ACLE special register intrinsicsLuke Cheeseman2015-06-151-0/+39
| | | | | | | | | | | | | in section 10.1, __arm_{w,r}sr{,p,64}. This includes arm_acle.h definitions with builtins and codegen to support these, the intrinsics are implemented by generating read/write_register calls which get appropriately lowered in the backend based on the register string provided. SemaChecking is also implemented to fault invalid parameters. Differential Revision: http://reviews.llvm.org/D9697 llvm-svn: 239737
* ARM: Add dbg builtin intrinsicYi Kong2014-08-261-0/+6
| | | | llvm-svn: 216452
* test/CodeGen: Don't rely on a value's number in check linesJustin Bogner2014-08-131-3/+4
| | | | | | | The tests in r215568 hard code a value as %0 in their checks. This isn't correct in asserts builds. llvm-svn: 215585
* ARM: Prefetch intrinsicsYi Kong2014-08-131-0/+11
| | | | llvm-svn: 215568
* ARM: Implement __builtin_arm_nop intrinsicYi Kong2014-07-141-0/+6
| | | | | | | | | | | This patch implements __builtin_arm_nop intrinsic for AArch32 and AArch64, which generates hint 0x0, the alias of NOP instruction. This intrinsic is necessary to implement ACLE __nop intrinsic. Differential Revision: http://reviews.llvm.org/D4495 llvm-svn: 212947
* [ARM] Implement ISB memory barrier intrinsicYi Kong2014-07-031-0/+1
| | | | | | | Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212277
* ARM: rename ARM builtins to use __builtin_arm prefixSaleem Abdulrasool2014-07-031-5/+5
| | | | | | | | | This corrects SVN r212196's naming change to use the proper prefix of `__builtin_arm_` instead of `__builtin_`. Thanks to Yi Kong for pointing out the incorrect naming! llvm-svn: 212253
* CodeGen: make target builtins support languagesSaleem Abdulrasool2014-07-021-5/+6
| | | | | | | | | | This extends the target builtin support to allow language specific annotations (i.e. LANGBUILTIN). This is to allow MSVC compatibility whilst retaining the ability to have EABI targets use a __builtin_ prefix. This is merely to allow uniformity in the EABI case where the unprefixed name is provided as an alias in the header. llvm-svn: 212196
* ARM: Support for __builtin_arm_rbit() intrinsic.Jim Grosbach2014-06-161-0/+6
| | | | | | | | Reverse the bits in a word. Maps to the RBIT instruction. rdar://9283021 llvm-svn: 211059
* CodeGen: complete ARM ACLE hint 8.4 supportSaleem Abdulrasool2014-05-041-0/+24
| | | | | | | Add support for the remaining hints from the ACLE. Although __dbg is listed as a hint, it is handled different, so it is not covered by this change. llvm-svn: 207930
* CodeGen: rename __builtin_arm_sevl to __sevlSaleem Abdulrasool2014-05-021-1/+1
| | | | | | | ACLE adds the __sevl() extension. Rename the hint from a custom name to the ACLE specified name. llvm-svn: 207829
* CodeGen: replace use of @llvm.arm.sevl with @llvm.arm.hintSaleem Abdulrasool2014-04-251-1/+1
| | | | | | | Use the new generic @llvm.arm.hint hint intrinsic rather than the specialised @llvm.arm.sevl hint instruction. llvm-svn: 207243
* add intrinsics: __builtin_arm_{dmb,dsb} for ARMWeiming Zhao2013-11-121-1/+5
| | | | llvm-svn: 194513
* [ARM] Add a builtin to allow you to use the 'sevl' instruction.Joey Gouly2013-10-021-0/+6
| | | | llvm-svn: 191816
* Implement __builtin_eh_return_data_regno() for ARM and MIPS.Logan Chien2013-02-231-0/+7
| | | | llvm-svn: 175954
* Tests: check for target availability for target-specific tests.Jim Grosbach2012-07-091-0/+1
| | | | | | | | Lots of tests are using an explicit target triple w/o first checking that the target is actually available. Add a REQUIRES clause to a bunch of them. This should hopefully unbreak bots which don't configure w/ all targets enabled. llvm-svn: 159949
* Builtins/ARM: __clear_cache doesn't seem to have a consistent prototype, declareDaniel Dunbar2010-07-161-1/+1
| | | | | | | the builtin as void __clear_cache(...) to workaround this, which appears to match what GCC does. llvm-svn: 108487
* Add a test to the previous commit.Rafael Espindola2010-06-081-1/+7
| | | | llvm-svn: 105596
* Revert changes r97693, r97700, and r97718.John McCall2010-03-041-2/+0
| | | | | | Our testing framework can't deal with disabled targets yet. llvm-svn: 97719
* XFAIL these tests on win32, since the win32 buildbot apparently disables allJohn McCall2010-03-041-0/+2
| | | | | | targets except X86. llvm-svn: 97718
* add framework for ARM builtins, Patch by Edmund Grimley Evans!Chris Lattner2010-03-031-0/+6
llvm-svn: 97656
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