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* [ARM] ACLE Chapter 9 intrinsicsSam Parker2017-05-041-4/+389
| | | | | | | | | | Implemented the remaining integer data processing intrinsics from the ARM ACLE v2.1 spec, such as parallel arithemtic and DSP style multiplications. Differential Revision: https://reviews.llvm.org/D32282 llvm-svn: 302131
* [ARM] Use generic bitreverse intrinsic, rather than ARM specific rbit.Chad Rosier2017-01-101-4/+4
| | | | | | The backend already supports lowering this intrinsic to a rbit instruction. llvm-svn: 291582
* [AArch64] Use generic bitreverse intrinsic, rather than AArch64 specific.Chad Rosier2017-01-101-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D28400 llvm-svn: 291574
* [ARM,AArch64] Fix __rev16l and __rev16ll intrinsicsOliver Stannard2015-11-161-10/+36
| | | | | | | | | | | | | | | | | | | | These two intrinsics are defined in arm_acle.h. __rev16l needs to rotate by 16 bits, bit it was actually rotating by 2 bits. For AArch64, where long is 64 bits, this would still be wrong. __rev16ll was incorrect, it reversed the bytes in each 32-bit word, rather than each 16-bit halfword. The correct implementation is to apply __rev16 to the top and bottom words of the 64-bit value. For AArch32 targets, these get compiled down to the hardware rev16 instruction at -O1 and above. For AArch64 targets, the 64-bit ones get compiled to two 32-bit rev16 instructions, because there is not currently a pattern for the 64-bit rev16 instruction. Differential Revision: http://reviews.llvm.org/D14609 llvm-svn: 253211
* [ARM] Replace hard coded metadata arguments in tests with a regex.Ranjeet Singh2015-06-171-17/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D10507 llvm-svn: 239932
* Wildcard out some SSA value names from the ACLE intrinsic test caseReid Kleckner2015-06-151-6/+6
| | | | llvm-svn: 239757
* This patch implements clang support for the ACLE special register intrinsicsLuke Cheeseman2015-06-151-0/+66
| | | | | | | | | | | | | in section 10.1, __arm_{w,r}sr{,p,64}. This includes arm_acle.h definitions with builtins and codegen to support these, the intrinsics are implemented by generating read/write_register calls which get appropriately lowered in the backend based on the register string provided. SemaChecking is also implemented to fault invalid parameters. Differential Revision: http://reviews.llvm.org/D9697 llvm-svn: 239737
* arm_acle: Implement data processing intrinsicsYi Kong2014-08-281-13/+95
| | | | | | | | | | | | | | | | | Summary: ACLE 2.0 section 9.2 defines the following "miscellaneous data processing intrinsics": `__clz`, `__cls`, `__ror`, `__rev`, `__rev16`, `__revsh` and `__rbit`. `__clz` has already been implemented in the arm_acle.h header file. The rest are not supported yet. This patch completes ACLE data processing intrinsics. Reviewers: t.p.northover, rengolin Reviewed By: rengolin Subscribers: aemerson, mroth, llvm-commits Differential Revision: http://reviews.llvm.org/D4983 llvm-svn: 216658
* arm_acle: Add mappings for dbg intrinsicYi Kong2014-08-261-0/+8
| | | | | | This completes all ACLE hint intrinsics. llvm-svn: 216453
* arm_acle: Implement swap intrinsicYi Kong2014-08-261-0/+10
| | | | | | | Insert the LDREX/STREX instruction sequence specified in ARM ACLE 2.0, as SWP instruction is deprecated since ARMv6. llvm-svn: 216446
* ARM: Add mappings for ACLE prefetch intrinsicsYi Kong2014-08-131-0/+29
| | | | | | | Implement __pld, __pldx, __pli and __plix builtin intrinsics as specified in ARM ACLE 2.0. llvm-svn: 215599
* [AArch64] Implement Clang CLI interface proposal about "-march".Kevin Qin2014-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Revert "Add default feature for CPUs on AArch64 target in Clang" at r210625. Then, all enabled feature will by passed explicitly by -target-feature in -cc1 option. 2. Get "-mfpu" deprecated. 3. Implement support of "-march". Usage is: -march=armv8-a+[no]feature For instance, "-march=armv8-a+neon+crc+nocrypto". Here "armv8-a" is necessary, and CPU names are not acceptable. Candidate features are fp, neon, crc and crypto. Where conflicting feature modifiers are specified, the right-most feature is used. 4. Implement support of "-mtune". Usage is: -march=CPU_NAME For instance, "-march=cortex-a57". This option will ONLY get micro-architectural feature enabled specifying to target CPU, like "+zcm" and "+zcz" for cyclone. Any architectural features WON'T be modified. 5. Change usage of "-mcpu" to "-mcpu=CPU_NAME+[no]feature", which is an alias to "-march={feature of CPU_NAME}+[no]feature" and "-mtune=CPU_NAME" together. Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option. llvm-svn: 213353
* ARM: Add ACLE memory barrier intrinsic mappingYi Kong2014-07-171-1/+23
| | | | llvm-svn: 213261
* ARM: Add NOP intrinsic mapping in arm_acle.hYi Kong2014-07-141-0/+8
| | | | llvm-svn: 212950
* tests: use a more precise target for testsSaleem Abdulrasool2014-07-121-2/+2
| | | | llvm-svn: 212892
* CodeGen: support hint intrinsics from ACLE on AArch64Saleem Abdulrasool2014-07-121-0/+37
| | | | | | | This adds support for the ACLE hint intrinsics on AArch64 similar to ARM. This is required to properly support ACLE on AArch64. llvm-svn: 212890
* Improve comments of ARM ACLE header file and testsYi Kong2014-07-121-3/+8
| | | | | | Include section number in ARM ACLE specification for easier navigation. llvm-svn: 212887
* Add the __qdbl intrinsic to the arm_acle.h headerRenato Golin2014-07-031-0/+9
| | | | | | Patch by: Moritz Roth llvm-svn: 212264
* Get arm_acle tests from r211962 workingAlp Toker2014-06-281-3/+2
| | | | llvm-svn: 211979
* Introduce arm_acle.h supporting existing LLVM builtin intrinsicsYi Kong2014-06-271-0/+129
Summary: This patch introduces ACLE header file, implementing extensions that can be directly mapped to existing Clang intrinsics. It implements for both AArch32 and AArch64. Reviewers: t.p.northover, compnerd, rengolin Reviewed By: compnerd, rengolin Subscribers: rnk, echristo, compnerd, aemerson, mroth, cfe-commits Differential Revision: http://reviews.llvm.org/D4296 llvm-svn: 211962
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