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| author | Ranjeet Singh <Ranjeet.Singh@arm.com> | 2015-06-17 19:56:30 +0000 |
|---|---|---|
| committer | Ranjeet Singh <Ranjeet.Singh@arm.com> | 2015-06-17 19:56:30 +0000 |
| commit | e8accef8660e5a5af47e612cccb74dbc95ca5bc7 (patch) | |
| tree | 4da4cc4cb11a413d2f6688b9780607ff7e4a500e /clang/test/CodeGen/arm_acle.c | |
| parent | 39026589b9e5688f4cec39195960e8dcaa13954e (diff) | |
| download | bcm5719-llvm-e8accef8660e5a5af47e612cccb74dbc95ca5bc7.tar.gz bcm5719-llvm-e8accef8660e5a5af47e612cccb74dbc95ca5bc7.zip | |
[ARM] Replace hard coded metadata arguments in tests with a regex.
Differential Revision: http://reviews.llvm.org/D10507
llvm-svn: 239932
Diffstat (limited to 'clang/test/CodeGen/arm_acle.c')
| -rw-r--r-- | clang/test/CodeGen/arm_acle.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c index d9d788b1ca9..a2eb900761b 100644 --- a/clang/test/CodeGen/arm_acle.c +++ b/clang/test/CodeGen/arm_acle.c @@ -339,8 +339,8 @@ uint32_t test_crc32cd(uint32_t a, uint64_t b) { /* 10.1 Special register intrinsics */ // ARM-LABEL: test_rsr -// AArch64: call i64 @llvm.read_register.i64(metadata !1) -// AArch32: call i32 @llvm.read_register.i32(metadata !3) +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]]) uint32_t test_rsr() { #ifdef __ARM_32BIT_STATE return __arm_rsr("cp1:2:c3:c4:5"); @@ -350,8 +350,8 @@ uint32_t test_rsr() { } // ARM-LABEL: test_rsr64 -// AArch64: call i64 @llvm.read_register.i64(metadata !1) -// AArch32: call i64 @llvm.read_register.i64(metadata !4) +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]]) uint64_t test_rsr64() { #ifdef __ARM_32BIT_STATE return __arm_rsr64("cp1:2:c3"); @@ -361,15 +361,15 @@ uint64_t test_rsr64() { } // ARM-LABEL: test_rsrp -// AArch64: call i64 @llvm.read_register.i64(metadata !2) -// AArch32: call i32 @llvm.read_register.i32(metadata !5) +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M1:[0-9]]]) +// AArch32: call i32 @llvm.read_register.i32(metadata ![[M4:[0-9]]]) void *test_rsrp() { return __arm_rsrp("sysreg"); } // ARM-LABEL: test_wsr -// AArch64: call void @llvm.write_register.i64(metadata !1, i64 %{{.*}}) -// AArch32: call void @llvm.write_register.i32(metadata !3, i32 %{{.*}}) +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}}) void test_wsr(uint32_t v) { #ifdef __ARM_32BIT_STATE __arm_wsr("cp1:2:c3:c4:5", v); @@ -379,8 +379,8 @@ void test_wsr(uint32_t v) { } // ARM-LABEL: test_wsr64 -// AArch64: call void @llvm.write_register.i64(metadata !1, i64 %{{.*}}) -// AArch32: call void @llvm.write_register.i64(metadata !4, i64 %{{.*}}) +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}}) void test_wsr64(uint64_t v) { #ifdef __ARM_32BIT_STATE __arm_wsr64("cp1:2:c3", v); @@ -390,15 +390,15 @@ void test_wsr64(uint64_t v) { } // ARM-LABEL: test_wsrp -// AArch64: call void @llvm.write_register.i64(metadata !2, i64 %{{.*}}) -// AArch32: call void @llvm.write_register.i32(metadata !5, i32 %{{.*}}) +// AArch64: call void @llvm.write_register.i64(metadata ![[M1:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i32(metadata ![[M4:[0-9]]], i32 %{{.*}}) void test_wsrp(void *v) { __arm_wsrp("sysreg", v); } -// AArch32: !3 = !{!"cp1:2:c3:c4:5"} -// AArch32: !4 = !{!"cp1:2:c3"} -// AArch32: !5 = !{!"sysreg"} +// AArch32: ![[M2]] = !{!"cp1:2:c3:c4:5"} +// AArch32: ![[M3]] = !{!"cp1:2:c3"} +// AArch32: ![[M4]] = !{!"sysreg"} -// AArch64: !1 = !{!"1:2:3:4:5"} -// AArch64: !2 = !{!"sysreg"} +// AArch64: ![[M0]] = !{!"1:2:3:4:5"} +// AArch64: ![[M1]] = !{!"sysreg"} |
