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* LLVM IR: Generate new-style byval-with-Type from ClangTim Northover2019-06-051-3/+3
| | | | | | | | | | | LLVM IR recently added a Type parameter to the byval Attribute, so that when pointers become opaque and no longer have an element type the information will still be present in IR. For now the Type parameter is optional (which is why Clang didn't need this change at the time), but it will become mandatory soon. llvm-svn: 362652
* [ARM] Remove redundant #if in test. NFCShoaib Meenai2018-05-011-4/+0
| | | | | | | | | | Both sides of this #if #include the same file. Drop the #if, leaving only the #include. Patch by Matt Glazar. Differential Revision: https://reviews.llvm.org/D45779 llvm-svn: 331305
* ARM: use ABI-specified alignment for byval parameters.Tim Northover2015-03-091-1/+1
| | | | | | | | | | | | | | | | When passing a type with large alignment byval, we were specifying the type's alignment rather than the alignment that the backend is actually capable of producing (ABIAlign). This would be OK (if odd) assuming the backend dealt with it prooperly, unfortunately it doesn't and trying to pass types with "byval align 16" can cause it to set fp incorrectly and trash the stack during the prologue. I'll be fixing that in a separate patch, but Clang should still be emitting IR that's as close to its intent as possible. rdar://20059039 llvm-svn: 231706
* ARM: Simplify PCS handling.Tim Northover2015-02-241-4/+4
| | | | | | | | The backend should now be able to handle all AAPCS rules based on argument type, which means Clang no longer has to duplicate the register-counting logic and the CodeGen can be significantly simplified. llvm-svn: 230349
* AArch64: simplify PCS mapping.Tim Northover2014-11-271-5/+5
| | | | | | | | | | | | Now that LLVM can count the registers needed to implement AAPCS rules, we don't need to duplicate that logic here. This means we can drop the explicit padding and also use more natural types in many cases (e.g. "struct { float arr[3]; }" used to end up as "[2 x double]" to avoid holes on the stack. The one wrinkle is that AAPCS va_arg was also using the register counting machinery. But the local replacement isn't too bad. llvm-svn: 222904
* This test also requires an aarch64 target.Eric Christopher2014-11-181-0/+1
| | | | llvm-svn: 222268
* ARM ABI: simplify decisions on whether args can be expanded.Tim Northover2014-11-071-7/+7
| | | | | | | | | | | | Homogeneous aggregates on AAPCS_VFP ARM need to be passed *without* being flattened (e.g. [2 x float] rather than "float, float") for various weird ABI reasons. However, this isn't the case for anything else; further, we know at the ABIArgInfo::getDirect callsites whether this flattening is allowed. So, we can get more unified ARM code, with a simpler Clang, by just using that knowledge directly. llvm-svn: 221559
* [ARM] Fix AAPCS regression caused by r211898Oliver Stannard2014-07-181-0/+5
| | | | | | | | | | | | | r211898 introduced a regression where a large struct, which would normally be passed ByVal, was causing padding to be inserted to prevent the backend from using some GPRs, in order to follow the AAPCS. However, the type of the argument was not being set correctly, so the backend cannot align 8-byte aligned struct types on the stack. The fix is to not insert the padding arguments when the argument is being passed ByVal. llvm-svn: 213359
* [ARM] Fix AAPCS non-compliance caused by very large structsOliver Stannard2014-06-271-0/+6
| | | | | | | | | | | | | | This is a fix to the code in clang which inserts padding arguments to ensure that the ARM backend can emit AAPCS-VFP compliant code. This code needs to track the number of registers which have been allocated in order to do this. When passing a very large struct (>64 bytes) by value, clang emits IR which takes a pointer to the struct, but the backend converts this back to passing the struct in registers and on the stack. The bug was that this was being considered by clang to only use one register, meaning that there were situations in which padding arguments were incorrectly emitted by clang. llvm-svn: 211898
* ARM: PCS non-compliance when struct is padded to avoid register/stack split, ↵Oliver Stannard2014-05-191-3/+8
| | | | | | | | | | and requires internal padding When we were padding a struct to avoid splitting it between registers and the stack, we were throwing away the type which the argument should be coerced to. llvm-svn: 209122
* Reapply r208417 (olista01 'ARM: HFAs must be passed in consecutive ↵James Molloy2014-05-091-12/+12
| | | | | | registers'). Bots are now pacified. llvm-svn: 208425
* Revert r208417 (olista01 'ARM: HFAs must be passed in consecutive ↵James Molloy2014-05-091-12/+12
| | | | | | registers'). This is a followon commit from r208413 which broke the LLVM bots. llvm-svn: 208422
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-091-12/+12
| | | | | | | This is the clang counterpart to 208413, which ensures that Homogeneous Floating-point Aggregates are passed in consecutive registers on ARM. llvm-svn: 208417
* ARM: Fix assertion caused by passing bitfield struct using ↵Oliver Stannard2014-05-071-2/+6
| | | | | | | | | | | | ABIArgInfo::getExpandWithPadding In cases where a struct must, according to the AAPCS, not be split between general purpose and floating point registers, we use ABIArgInfo::getExpandWithPadding to add the padding arguments. However, ExpandWithPadding does not work if the struct contains bitfields, so we instead must use ABIArgInfo::getDirect. llvm-svn: 208185
* [ARM64] Allow the disabling of NEON and crypto instructions. Update tests to ↵James Molloy2014-04-161-1/+1
| | | | | | pass -target-feature +neon. llvm-svn: 206394
* ARM64: initial clang support commit.Tim Northover2014-03-291-0/+17
| | | | | | | | | | | This adds Clang support for the ARM64 backend. There are definitely still some rough edges, so please bring up any issues you see with this patch. As with the LLVM commit though, we think it'll be more useful for merging with AArch64 from within the tree. llvm-svn: 205100
* ARM: Correct alignment of structs passed as byval pointerOliver Stannard2014-03-121-1/+1
| | | | | | | | | | When a struct has bitfields overlapping with other members (as required by the AAPCS), clang uses a packed struct to represent this. If such a struct is large enough for clang to pass it as a byval pointer (>64 bytes), we need to set the alignment of the argument to match the original type. llvm-svn: 203660
* AAPCS: Do not split structs after CPRC allocated on stackOliver Stannard2014-02-111-0/+10
| | | | | | | | | | According to the AAPCS, we can split structs between GPRs and the stack, except for when an argument has already been allocated on the stack. This can occur when a large number of floating-point arguments fill up the VFP registers, and are alllocated on the stack before the general-purpose argument registers are full. llvm-svn: 201137
* [ARM] Fix AAPCS-VFP non-compliance when returning HFA from variadic functions.Amara Emerson2014-01-281-0/+5
| | | | | | | | | Arguments and return values must always be marshalled as for the base AAPCS when the callee is a variadic function. Patch by Oliver Stannard! llvm-svn: 200307
* CHECK-LABEL-ify some code gen tests to improve diagnostic experience when ↵Stephen Lin2013-08-151-1/+1
| | | | | | tests fail. llvm-svn: 188447
* Properly factor Native Client defines to support NaCl as an OSDerek Schuff2012-10-111-0/+6
| | | | | | with x86/ARM architecture llvm-svn: 165722
* ARM: enable struct byval for AAPCS-VFP.Manman Ren2012-08-131-0/+4
| | | | | | rdar://9877866 llvm-svn: 161790
* Add "long double" to permitted list of ARM complex homogeneous aggregates.Tim Northover2012-07-201-0/+7
| | | | | | | Under AAPCS, long double is the same as double, which means it should be allowed as part of a homogeneous aggregate. llvm-svn: 160586
* Tests: check for target availability for target-specific tests.Jim Grosbach2012-07-091-0/+1
| | | | | | | | Lots of tests are using an explicit target triple w/o first checking that the target is actually available. Add a REQUIRES clause to a bunch of them. This should hopefully unbreak bots which don't configure w/ all targets enabled. llvm-svn: 159949
* Check for homogeneous aggregate return values with ARM's AAPCS-VFP ABI.Bob Wilson2011-11-021-4/+4
| | | | llvm-svn: 143530
* Handle "homogeneous aggregates" as required by the ARM AAPCS-VFP ABI.Bob Wilson2011-08-031-0/+82
A homogeneous aggregate is an aggregate data structure where after flattening any nesting there are 1 to 4 elements of the same base type that is either a float, double, or Neon vector. All Neon vectors of the same size, either 64 or 128 bits, are treated as equivalent for this purpose. When using the AAPCS-VFP ABI, check for homogeneous aggregates and pass them as arguments by expanding them into a sequence of their base types. This requires extending the existing support for expanded arguments to handle not only structs, but also constant arrays and complex types. llvm-svn: 136767
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