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* [clang] Fixed x86 cpuid NSC signatureRaphael Isemann2019-08-101-2/+2
| | | | | | | | | | | | | | | | | | Summary: The signature "Geode by NSC" for NSC vendor is wrong. In lib/Headers/cpuid.h, signature_NSC_edx and signature_NSC_ecx constants are inverted (cpuid signature order is ebx # edx # ecx). Reviewers: teemperor, rsmith, craig.topper Reviewed By: teemperor, craig.topper Subscribers: craig.topper, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D65978 llvm-svn: 368510
* [X86] Add ENQCMD instructionsPengfei Wang2019-06-061-0/+1
| | | | | | | | | | | | For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Patch by Tianqing Wang (tianqing) Differential Revision: https://reviews.llvm.org/D62282 llvm-svn: 362685
* Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper ↵Luo, Yuanke2019-05-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Lake Summary: 1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake; 2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision. For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Patch by LiuTianle Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon Reviewed By: craig.topper Subscribers: mgorny, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60552 llvm-svn: 360018
* Move the builtin headers to use the new license file header.Chandler Carruth2019-04-081-17/+3
| | | | | | | | | | | | | | | | | | Summary: These all had somewhat custom file headers with different text from the ones I searched for previously, and so I missed them. Thanks to Hal and Kristina and others who prompted me to fix this, and sorry it took so long. Reviewers: hfinkel Subscribers: mcrosier, javed.absar, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60406 llvm-svn: 357941
* [x86] invpcid intrinsicGabor Buella2018-05-251-0/+1
| | | | | | | | | | | | An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 llvm-svn: 333256
* [X86] ptwrite intrinsicGabor Buella2018-05-101-0/+3
| | | | | | | | | | Reviewers: craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46540 llvm-svn: 331962
* [x86] Introduce the pconfig intrinsicGabor Buella2018-05-081-0/+1
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46431 llvm-svn: 331740
* [X86] directstore and movdir64b intrinsicsGabor Buella2018-05-011-0/+2
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45984 llvm-svn: 331249
* [X86] WaitPKG intrinsicsGabor Buella2018-04-201-0/+1
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45254 llvm-svn: 330463
* [X86] Introduce cldemote intrinsicGabor Buella2018-04-131-0/+1
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45257 llvm-svn: 329993
* [x86] wbnoinvd intrinsicGabor Buella2018-04-111-1/+2
| | | | | | | | | | | | | | The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43817 llvm-svn: 329848
* [X86] Fix typo in cpuid.h, bit_AVX51SER->bit_AVX512ER.Craig Topper2018-03-061-1/+1
| | | | llvm-svn: 326807
* [X86] Add more CPUID bits to cpuid.h to match gcc and support icelake features.Craig Topper2017-12-201-5/+14
| | | | llvm-svn: 321129
* [X86] Add more feature flag bit defines to cpuid.h for gcc compatibility.Craig Topper2017-07-091-3/+61
| | | | llvm-svn: 307507
* [X86] Add __get_cpuid_count to cpuid.h. Update __get_cpuid to check the ↵Craig Topper2017-07-091-17/+37
| | | | | | | | maximum level support before accessing the leaf. Rename level to leaf everywhere. This matches gcc behavior. llvm-svn: 307506
* Add more gcc compatibility names to clang's cpuid.hDimitry Andric2016-07-311-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some cpuid bit defines are named slightly different from how gcc's cpuid.h calls them. Define a few more compatibility names to appease software built for gcc: * `bit_PCLMUL` alias of `bit_PCLMULQDQ` * `bit_SSE4_1` alias of `bit_SSE41` * `bit_SSE4_2` alias of `bit_SSE42` * `bit_AES` alias of `bit_AESNI` * `bit_CMPXCHG8B` alias of `bit_CX8` While here, add the misssing 29th bit, `bit_F16C` (which is how gcc calls this bit). Reviewers: joerg, rsmith Subscribers: bruno, cfe-commits Differential Revision: https://reviews.llvm.org/D22010 llvm-svn: 277307
* Fix trailing commas in AMD define.Joerg Sonnenberger2014-10-011-3/+3
| | | | llvm-svn: 218825
* Add the various signature macros.Joerg Sonnenberger2014-10-011-0/+54
| | | | llvm-svn: 218824
* Rename bit_RDRAND to bit_RDRND to match GCC's version of this header.Joerg Sonnenberger2014-10-011-1/+1
| | | | llvm-svn: 218823
* Fix bugs in cpuid.h.Akira Hatanaka2014-09-201-15/+13
| | | | | | | | | | | | | | | This commit makes two changes: - Remove the push and pop instructions that were saving and restoring %ebx before and after cpuid in 32-bit pic mode. We were doing this to ensure we don't lose the GOT address in pic register %ebx, but this isn't necessary because the GOT address is kept in a virtual register. - In 64-bit mode, preserve base register %rbx around cpuid. This fixes PR20311 and rdar://problem/17686779. llvm-svn: 218173
* Add bit_FXSAVE as an alias for bit_FXSR, for gcc compat.Nico Weber2013-12-161-0/+1
| | | | llvm-svn: 197399
* This patch implements __get_cpuid_max() as an inline and __cpuid() andRoman Divacky2013-07-191-2/+124
| | | | | | | | | | | | | __cpuid_count() as macros to be compatible with GCC's cpuid.h. It also adds bit_<foo> constants for the various feature bits as described in version 039 (May 2011) of Intel's SDM Volume 2 in the description of the CPUID instruction. The list of bit_<foo> constants is a bit exhaustive (GCC doesn't do near this many). More bits could be added from a newer version of SDM if desired. Patch by John Baldwin! llvm-svn: 186696
* Add tests that build modules for our builtin headers, and fix two buglets ↵Richard Smith2013-04-041-3/+3
| | | | | | exposed by doing so. llvm-svn: 178736
* PR14964: intrinsic headers using non-reserved identifiersDavid Blaikie2013-01-161-4/+5
| | | | | | | | | | | | | | | | Several of the intrinsic headers were using plain non-reserved identifiers. C++11 17.6.4.3.2 [global.names] p1 reservers names containing a double begining with an underscore followed by an uppercase letter for any use. I think I got them all, but open to being corrected. For the most part I didn't bother updating function-like macro parameter names because I don't believe they're subject to any such collission - though some function-like macros already follow this convention (I didn't update them in part because the churn was more significant as several function-like macros use the double underscore prefixed version of the same name as a parameter in their implementation) llvm-svn: 172666
* Make cpuid.h actually work with -std=c99 <rdar://problem/12552716>.Douglas Gregor2012-11-051-1/+1
| | | | | | | | While we're here, extend the module map to cover most of the newly-added instrinsic headers. Only wmmintrin.h is missing, because it needs to be split into AES/PCLMUL subheaders (as a separate commit). llvm-svn: 167398
* Fix comment.Rafael Espindola2011-11-281-1/+1
| | | | llvm-svn: 145271
* Error on non x86 architectures.Rafael Espindola2011-11-271-0/+4
| | | | llvm-svn: 145185
* Fix file name in comments.Rafael Espindola2011-11-271-1/+1
| | | | llvm-svn: 145184
* Add the minimum implementation of cpuid.h. This works on "modern" intel cpusRafael Espindola2011-11-261-0/+29
and on clang, which seams to handled "=b" correctly even when ebx is the PIC register. llvm-svn: 145149
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