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* [X86] Add clang support for X86 flag output parameters.Nirav Dave2019-02-141-0/+52
| | | | | | | | | | | | | | Summary: Add frontend support and expected flags for X86 inline assembly flag parameters. Reviewers: craig.topper, rnk, echristo Subscribers: eraman, nickdesaulniers, void, llvm-commits Differential Revision: https://reviews.llvm.org/D57394 llvm-svn: 354053
* [PowerPC] Stop defining _ARCH_PWR6X on POWER7 and upHubert Tong2019-02-131-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The predefined macro `_ARCH_PWR6X` is associated with GCC's `-mcpu=power6x` option, which enables generation of P6 "raw mode" instructions such as `mftgpr`. Later POWER processors build upon the "architected mode", not the raw one. `_ARCH_PWR6X` should not be defined for these later processors. Fixes PR#40236. Reviewers: echristo, hfinkel, kbarton, nemanjai, wschmidt Reviewed By: hfinkel Subscribers: jsji, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D58128 llvm-svn: 353975
* [Headers][mips] Add `__attribute__((__mode__(__unwind_word__)))` to the ↵Simon Atanasyan2019-02-132-0/+10
| | | | | | | | | | | | | | | | | | _Unwind_Word / _Unwind_SWord definitions The rationale of this change is to fix _Unwind_Word / _Unwind_SWord definitions for MIPS N32 ABI. This ABI uses 32-bit pointers, but _Unwind_Word and _Unwind_SWord types are eight bytes long. # The __attribute__((__mode__(__unwind_word__))) is added to the type definitions. It makes them equal to the corresponding definitions used by GCC and allows to override types using `getUnwindWordWidth` function. # The `getUnwindWordWidth` virtual function override in the `MipsTargetInfo` class and provides correct type size values. Differential revision: https://reviews.llvm.org/D58165 llvm-svn: 353965
* long double is double on OpenBSD/NetBSD/PPC.Brad Smith2019-02-111-1/+7
| | | | | | Patch by George Koehler. llvm-svn: 353656
* [AMDGPU] Split dot-insts featureStanislav Mekhanoshin2019-02-091-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D57972 llvm-svn: 353588
* bpf: teach BPF driver about the new CPU "v3"Jiong Wang2019-02-071-1/+1
| | | | | | | | | This patch simply teach BPF driver about the new CPU "v3" introduced in LLVM backend. Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 353479
* [WebAssembly] Add atomics target optionHeejin Ahn2019-02-062-0/+15
| | | | | | | | | | | | Reviewers: tlively Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57798 llvm-svn: 353260
* [DEBUG_INFO][NVPTX] Generate correct data about variable address class.Alexey Bataev2019-02-051-0/+24
| | | | | | | | | | | | | | | | | | | | | Summary: Added ability to generate correct debug info data about the variable address class. Currently, for all the locals and globals the default values are used, ADDR_local_space(6) for locals and ADDR_global_space(5) for globals. The values are taken from the table in https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf. We need to emit correct data for address classes of, at least, shared and constant globals. Currently, all these variables are treated by the cuda-gdb debugger as the variables in the global address space and, thus, it require manual data type casting. Reviewers: echristo, probinson Subscribers: jholewinski, aprantl, cfe-commits Differential Revision: https://reviews.llvm.org/D57162 llvm-svn: 353204
* Do not copy long double and 128-bit fp format from aux target for AMDGPUYaxun Liu2019-01-311-0/+11
| | | | | | | | | | | | | | | rC352620 caused regressions because it copied floating point format from aux target. floating point format decides whether extended long double is supported. It is x86_fp80 on x86 but IEEE double on amdgcn. Document usage of long doubel type in HIP programming guide https://github.com/ROCm-Developer-Tools/HIP/pull/890 Differential Revision: https://reviews.llvm.org/D57527 llvm-svn: 352801
* [WebAssembly] Add bulk memory target featureThomas Lively2019-01-312-5/+24
| | | | | | | | | | | | Summary: Also clean up some preexisting target feature code. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, jfb Differential Revision: https://reviews.llvm.org/D57495 llvm-svn: 352793
* [HIP] Fix size_t for MSVC environmentYaxun Liu2019-01-302-0/+6
| | | | | | | | | | | In 64 bit MSVC environment size_t is defined as unsigned long long. In single source language like HIP, data layout should be consistent in device and host compilation, therefore copy data layout controlling fields from Aux target for AMDGPU target. Differential Revision: https://reviews.llvm.org/D56318 llvm-svn: 352620
* Disable _Float16 for non ARM/SPIR TargetsErich Keane2019-01-253-0/+3
| | | | | | | | | | | | | | As Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2019-January/129543.html There are problems exposing the _Float16 type on architectures that haven't defined the ABI/ISel for the type yet, so we're temporarily disabling the type and making it opt-in. Differential Revision: https://reviews.llvm.org/D57188 Change-Id: I5db7366dedf1deb9485adb8948b1deb7e612a736 llvm-svn: 352221
* [MSP430] Ajust f32/f64 alignment according to MSP430 EABIAnton Korobeynikov2019-01-251-0/+6
| | | | | | | | Patch by Kristina Bessonova! Differential Revision: https://reviews.llvm.org/D57015 llvm-svn: 352177
* [WebAssembly] Add a __wasi__ target macroDan Gohman2019-01-241-1/+17
| | | | | | | | | This adds a `__wasi__` macro for the wasi OS, similar to `__linux__` etc. for other OS's. Differential Revision: https://reviews.llvm.org/D57155 llvm-svn: 352105
* [WebAssembly] Support __float128Dan Gohman2019-01-241-0/+3
| | | | | | | | This enables support for the "__float128" keyword. Differential Revision: https://reviews.llvm.org/D57154 llvm-svn: 352100
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-1946-184/+138
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Convert two more files that were using Windows line endings and removeChandler Carruth2019-01-191-1/+1
| | | | | | | a stray single '\r' from one file. These are the last line ending issues I can find in the files containing parts of LLVM's file headers. llvm-svn: 351634
* Revert "Clang side support for @cc assembly operands."Nirav Dave2019-01-181-52/+0
| | | | llvm-svn: 351561
* Clang side support for @cc assembly operands.Nirav Dave2019-01-181-0/+52
| | | | llvm-svn: 351559
* [Nios2] Remove Nios2 backendCraig Topper2019-01-152-207/+0
| | | | | | | | As mentioned here http://lists.llvm.org/pipermail/llvm-dev/2019-January/129121.html This backend is incomplete and has not been maintained in several months. Differential Revision: https://reviews.llvm.org/D56690 llvm-svn: 351230
* [WebAssembly] Add unimplemented-simd128 feature, gate builtinsThomas Lively2019-01-102-10/+54
| | | | | | | | | | | Summary: Depends on D56501. Also adds a macro define `__wasm_unimplemented_simd128__` for feature detection of unimplemented SIMD builtins. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, kristina, cfe-commits, rrwinterton llvm-svn: 350909
* [AMDGPU] Separate feature dot-instsStanislav Mekhanoshin2019-01-101-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D56525 llvm-svn: 350794
* Android is not GNU, so don't claim that it is.Dan Albert2019-01-081-1/+2
| | | | | | | | | | | | Reviewers: pirama, srhines Reviewed By: srhines Subscribers: kristina, cfe-commits Differential Revision: https://reviews.llvm.org/D55953 llvm-svn: 350664
* Replace getOS() == llvm::Triple::*BSD with isOS*BSD() [NFCI]Michal Gorny2018-12-206-16/+16
| | | | | | | | | | | | Replace multiple comparisons of getOS() value with FreeBSD, NetBSD, OpenBSD and DragonFly with matching isOS*BSD() methods. This should improve the consistency of coding style without changing the behavior. Direct getOS() comparisons were left whenever used in switch or switch- like context. Differential Revision: https://reviews.llvm.org/D55916 llvm-svn: 349752
* Basic: make `int_least64_t` and `int_fast64_t` match on DarwinSaleem Abdulrasool2018-12-121-0/+9
| | | | | | | | | The Darwin targets use `int64_t` and `uint64_t` to define the `int_least64_t` and `int_fast64_t` types. The underlying type is actually a `long long`. Match the types to allow the printf specifiers to work properly and have the compiler vended macros match the implementation on the target. llvm-svn: 348939
* Move CodeGenOptions from Frontend to BasicRichard Trieu2018-12-111-1/+1
| | | | | | Basic uses CodeGenOptions and should not depend on Frontend. llvm-svn: 348827
* [PowerPC] VSX register support for inline assemblyKang Zhang2018-12-072-0/+32
| | | | | | | | | | | | Summary: The patch is to add the VSX register support for inline assembly. After this patch, we can use VSX register in inline assembly clobber list without error. Reviewed By: jsji, nemanjai Differential Revision: https://reviews.llvm.org/D55192 llvm-svn: 348572
* ARM, AArch64: support `__attribute__((__swiftcall__))`Saleem Abdulrasool2018-12-062-0/+2
| | | | | | | | | | Support the Swift calling convention on Windows ARM and AArch64. Both of these conform to the AAPCS, AAPCS64 calling convention, and LLVM has been adjusted to account for the register usage. Ensure that the frontend passes this into the backend. This allows the swift runtime to be built for Windows. llvm-svn: 348454
* [Hexagon] Add support for Hexagon V66Krzysztof Parzyszek2018-12-051-1/+4
| | | | llvm-svn: 348415
* [Haiku] Support __float128 for x86 and x86_64Kristina Brooks2018-12-051-0/+10
| | | | | | | | | | | | | This patch addresses a compilation error with clang when running in Haiku being unable to compile code using float128 (throws compilation error such as 'float128 is not supported on this target'). Patch by kallisti5 (Alexander von Gluck IV) Differential Revision: https://reviews.llvm.org/D54901 llvm-svn: 348368
* [SystemZ] Do not support __float128Ulrich Weigand2018-12-041-1/+0
| | | | | | | | | | | | | As of rev. 268898, clang supports __float128 on SystemZ. This seems to have been in error. GCC has never supported __float128 on SystemZ, since the "long double" type on the platform is already IEEE-128. (GCC only supports __float128 on platforms where "long double" is some other data type.) For compatibility reasons this patch removes __float128 on SystemZ again. The test case is updated accordingly. llvm-svn: 348247
* Add Hurd target to Clang driver (2/2)Kristina Brooks2018-11-291-0/+23
| | | | | | | | | | | | | | | This adds Hurd toolchain support to Clang's driver in addition to handling translating the triple from Hurd-compatible form to the actual triple registered in LLVM. (Phabricator was stripping the empty files from the patch so I manually created them) Patch by sthibaul (Samuel Thibault) Differential Revision: https://reviews.llvm.org/D54379 llvm-svn: 347833
* [clang][ARC] Add ARCTargetInfoTatyana Krasnukha2018-11-272-0/+99
| | | | | | | | Based-on-patch-by: Pete Couperus <petecoup@synopsys.com> Differential Revision: https://reviews.llvm.org/D53100 llvm-svn: 347699
* [X86] Add -march=cascadelake support in clang.Craig Topper2018-11-271-2/+10
| | | | | | | | | | This is skylake-avx512 with the addition of avx512vnni ISA. Patch by Jianping Chen Differential Revision: https://reviews.llvm.org/D54792 llvm-svn: 347682
* [AArch64] Add aarch64_vector_pcs function attribute to ClangSander de Smalen2018-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | This is the Clang patch to complement the following LLVM patches: https://reviews.llvm.org/D51477 https://reviews.llvm.org/D51479 More information describing the vector ABI and procedure call standard can be found here: https://developer.arm.com/products/software-development-tools/\ hpc/arm-compiler-for-hpc/vector-function-abi Patch by Kerry McLaughlin. Reviewed By: rjmccall Differential Revision: https://reviews.llvm.org/D54425 llvm-svn: 347571
* Fix clang -Wimplicit-fallthrough warnings across llvm, NFCReid Kleckner2018-11-012-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch should not introduce any behavior changes. It consists of mostly one of two changes: 1. Replacing fall through comments with the LLVM_FALLTHROUGH macro 2. Inserting 'break' before falling through into a case block consisting of only 'break'. We were already using this warning with GCC, but its warning behaves slightly differently. In this patch, the following differences are relevant: 1. GCC recognizes comments that say "fall through" as annotations, clang doesn't 2. GCC doesn't warn on "case N: foo(); default: break;", clang does 3. GCC doesn't warn when the case contains a switch, but falls through the outer case. I will enable the warning separately in a follow-up patch so that it can be cleanly reverted if necessary. Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu Differential Revision: https://reviews.llvm.org/D53950 llvm-svn: 345882
* Add LLVM_FALLTHROUGH annotation after switchReid Kleckner2018-11-011-0/+1
| | | | | | | | | | | This silences a -Wimplicit-fallthrough warning from clang. GCC does not appear to warn when the case body ends in a switch. This is a somewhat surprising but intended fallthrough that I pulled out from my mechanical patch. The code intends to handle 'Yi' and related constraints as the 'x' constraint. llvm-svn: 345873
* [Clang][PowerPC] Support constraint 'wi' in asmLi Jia He2018-11-011-0/+1
| | | | | | | | | | From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345809
* NFC: Remove the ObjC1/ObjC2 distinction from clang (and related projects)Erik Pilkington2018-10-301-1/+1
| | | | | | | | | | We haven't supported compiling ObjC1 for a long time (and never will again), so there isn't any reason to keep these separate. This patch replaces LangOpts::ObjC1 and LangOpts::ObjC2 with LangOpts::ObjC. Differential revision: https://reviews.llvm.org/D53547 llvm-svn: 345637
* [AArch64] Implement FP16FML intrinsicsBryan Chan2018-10-252-0/+7
| | | | | | | | | | | | | Generate the FP16FML intrinsics into arm_neon.h (AArch64 only for now). Add two new type modifiers to NeonEmitter to handle the new prototypes. Define __ARM_FEATURE_FP16FML when +fp16fml is enabled and guard the intrinsics with the macro in arm_neon.h. Based on a patch by Gao Yiling. Differential Revision: https://reviews.llvm.org/D53633 llvm-svn: 345344
* Implement Function Multiversioning for Non-ELF Systems.Erich Keane2018-10-251-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Similar to how ICC handles CPU-Dispatch on Windows, this patch uses the resolver function directly to forward the call to the proper function. This is not nearly as efficient as IFuncs of course, but is still quite useful for large functions specifically developed for certain processors. This is unfortunately still limited to x86, since it depends on __builtin_cpu_supports and __builtin_cpu_is, which are x86 builtins. The naming for the resolver/forwarding function for cpu-dispatch was taken from ICC's implementation, which uses the unmodified name for this (no mangling additions). This is possible, since cpu-dispatch uses '.A' for the 'default' version. In 'target' multiversioning, this function keeps the '.resolver' extension in order to keep the default function keeping the default mangling. Change-Id: I4731555a39be26c7ad59a2d8fda6fa1a50f73284 Differential Revision: https://reviews.llvm.org/D53586 llvm-svn: 345298
* Add gfx909 to GPU ArchTim Renouf2018-10-241-0/+1
| | | | | | | | Subscribers: jholewinski, cfe-commits Differential Revision: https://reviews.llvm.org/D53558 llvm-svn: 345198
* AMDGPU: Handle gfx909 in AMDGPUTargetInfo::initFeatureMapKonstantin Zhuravlyov2018-10-241-0/+1
| | | | | | + add required tests llvm-svn: 345181
* Add gfx904 and gfx906 to GPU ArchYaxun Liu2018-10-231-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D53472 llvm-svn: 344996
* [X86] Remove 'rtm' feature from KNL.Craig Topper2018-10-231-1/+0
| | | | | | | | I'm unsure if KNL has this feature, but the backend never thought it did, only clang did. The predefined-arch-macros test lost the check for __RTM__ on KNL when it was removed Skylake CPUs in r344117. I think we want to drop it from KNL for consistency with Skylake anyway regardless of how we got here. llvm-svn: 344978
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-11/+4
| | | | llvm-svn: 344786
* [AArch64] Define __ELF__ for aarch64-none-elf and other similar triples.Eli Friedman2018-10-171-3/+2
| | | | | | | | "aarch64-none-elf" is commonly used for AArch64 baremetal toolchains. Differential Revision: https://reviews.llvm.org/D53348 llvm-svn: 344710
* [mips] Fix handling of GNUABIN32 environment in a target tripleSimon Atanasyan2018-10-151-1/+6
| | | | | | | | | | | | The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
* [X86] Remove FeatureRTM from Skylake processor listCraig Topper2018-10-101-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There are a LOT of Skylakes and later without TSX-NI. Examples: - SKL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3-20-GHz- - KBL: https://ark.intel.com/products/97540/Intel-Core-i7-7560U-Processor-4M-Cache-up-to-3-80-GHz- - KBL-R: https://ark.intel.com/products/149091/Intel-Core-i7-8565U-Processor-8M-Cache-up-to-4-60-GHz- - CNL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3_20-GHz This feature seems to be present only on high-end desktop and server chips (I can't find any SKX without). This commit leaves it disabled for all processors, but can be re-enabled for specific builds with -mrtm. Matches https://reviews.llvm.org/D53041 Patch by Thiago Macieira Reviewers: erichkeane, craig.topper Reviewed By: craig.topper Subscribers: lebedev.ri, cfe-commits Differential Revision: https://reviews.llvm.org/D53042 llvm-svn: 344117
* Introduce code_model macrosAli Tamur2018-10-081-0/+5
| | | | | | | | | | | | | | | | | | | Summary: gcc defines macros such as __code_model_small_ based on the user passed command line flag -mcmodel. clang accepts a flag with the same name and similar effects, but does not generate any macro that the user can use. This cl narrows the gap between gcc and clang behaviour. However, achieving full compatibility with gcc is not trivial: The set of valid values for mcmodel in gcc and clang are not equal. Also, gcc defines different macros for different architectures. In this cl, we only tackle an easy part of the problem and define the macro only for x64 architecture. When the user does not specify a mcmodel, the macro for small code model is produced, as is the case with gcc. Reviewers: compnerd, MaskRay Reviewed By: MaskRay Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D52920 llvm-svn: 344000
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