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* [COFF, ARM64] Align global symbol by size for ARM64 MSVC ABITom Tan2019-05-021-0/+17
| | | | | | | | | | | | | | | | | According to alignment section in below ARM64 ABI document, MSVC could increase alignment of global data based on its total size. Clang doesn't do this. Compile the same symbol into different alignments by Clang and MSVC could cause link error because some instruction encodings, like 64-bit LDR/STR with immediate, require the target to be 8 bytes aligned, and linker could choose code stream with such LDR/STR instruction from MSVC and 4 bytes aligned data from Clang into final image, which actually cannot be linked together (see https://bugs.llvm.org/show_bug.cgi?id=41506 for more details). https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019#alignment Differential Revision: https://reviews.llvm.org/D61225 llvm-svn: 359744
* [AArch64] Initialize HasMTEVitaly Buka2019-04-271-0/+1
| | | | llvm-svn: 359366
* [AArch64] Add support for MTE intrinsicsJaved Absar2019-04-261-0/+5
| | | | | | | | | | | | This provides intrinsics support for Memory Tagging Extension (MTE), which was introduced with the Armv8.5-a architecture. These intrinsics are available when __ARM_FEATURE_MEMORY_TAGGING is defined. Each intrinsic is described in detail in the ACLE Q1 2019 documentation: https://developer.arm.com/docs/101028/latest Reviewed By: Tim Nortover, David Spickett Differential Revision: https://reviews.llvm.org/D60485 llvm-svn: 359348
* Disable _Float16 for non ARM/SPIR TargetsErich Keane2019-01-251-0/+1
| | | | | | | | | | | | | | As Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2019-January/129543.html There are problems exposing the _Float16 type on architectures that haven't defined the ABI/ISel for the type yet, so we're temporarily disabling the type and making it opt-in. Differential Revision: https://reviews.llvm.org/D57188 Change-Id: I5db7366dedf1deb9485adb8948b1deb7e612a736 llvm-svn: 352221
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Replace getOS() == llvm::Triple::*BSD with isOS*BSD() [NFCI]Michal Gorny2018-12-201-2/+2
| | | | | | | | | | | | Replace multiple comparisons of getOS() value with FreeBSD, NetBSD, OpenBSD and DragonFly with matching isOS*BSD() methods. This should improve the consistency of coding style without changing the behavior. Direct getOS() comparisons were left whenever used in switch or switch- like context. Differential Revision: https://reviews.llvm.org/D55916 llvm-svn: 349752
* ARM, AArch64: support `__attribute__((__swiftcall__))`Saleem Abdulrasool2018-12-061-0/+1
| | | | | | | | | | Support the Swift calling convention on Windows ARM and AArch64. Both of these conform to the AAPCS, AAPCS64 calling convention, and LLVM has been adjusted to account for the register usage. Ensure that the frontend passes this into the backend. This allows the swift runtime to be built for Windows. llvm-svn: 348454
* [AArch64] Add aarch64_vector_pcs function attribute to ClangSander de Smalen2018-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | This is the Clang patch to complement the following LLVM patches: https://reviews.llvm.org/D51477 https://reviews.llvm.org/D51479 More information describing the vector ABI and procedure call standard can be found here: https://developer.arm.com/products/software-development-tools/\ hpc/arm-compiler-for-hpc/vector-function-abi Patch by Kerry McLaughlin. Reviewed By: rjmccall Differential Revision: https://reviews.llvm.org/D54425 llvm-svn: 347571
* [AArch64] Implement FP16FML intrinsicsBryan Chan2018-10-251-0/+6
| | | | | | | | | | | | | Generate the FP16FML intrinsics into arm_neon.h (AArch64 only for now). Add two new type modifiers to NeonEmitter to handle the new prototypes. Define __ARM_FEATURE_FP16FML when +fp16fml is enabled and guard the intrinsics with the macro in arm_neon.h. Based on a patch by Gao Yiling. Differential Revision: https://reviews.llvm.org/D53633 llvm-svn: 345344
* [AArch64] Define __ELF__ for aarch64-none-elf and other similar triples.Eli Friedman2018-10-171-3/+2
| | | | | | | | "aarch64-none-elf" is commonly used for AArch64 baremetal toolchains. Differential Revision: https://reviews.llvm.org/D53348 llvm-svn: 344710
* [ARM64] [Windows] Follow MS X86_64 C++ ABI when passing structsSanjin Sijaric2018-07-261-0/+5
| | | | | | | | | | | | | | | | | Summary: Microsoft's C++ object model for ARM64 is the same as that for X86_64. For example, small structs with non-trivial copy constructors or virtual function tables are passed indirectly. Currently, they are passed in registers when compiled with clang. Reviewers: rnk, mstorsjo, TomTan, haripul, javed.absar Reviewed By: rnk, mstorsjo Subscribers: kristof.beyls, chrib, llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D49770 llvm-svn: 338076
* [AArch64] Define TARGET_HEADER_BUILTINMartin Storsjo2018-07-181-0/+2
| | | | | | | Without it, the new intrinsics became available for all language variants. This was missed in SVN r337327. llvm-svn: 337352
* By popular demand, switch in64_t on NetBSD/AArch64 and NetBSD/PowerPC64Joerg Sonnenberger2018-07-171-5/+2
| | | | | | to long for consistency with other 64bit platforms. llvm-svn: 337271
* [AAch64] Add the __ARM_FEATURE_DOTPROD macro definitionJunmo Park2018-04-171-0/+6
| | | | | | | | | This matches what GCC does. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/aarch64/aarch64-c.c Differential Revision: https://reviews.llvm.org/D45544 llvm-svn: 330229
* [AArch64]: Add support for parsing rN registers.Manoj Gupta2018-03-291-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Allow rN registers to be simply parsed as correspoing xN registers. The "register ... asm("rN")" is an command to the compiler's register allocator, not an operand to any individual assembly instruction. GCC documents this syntax as "...the name of the register that should be used." This is needed to support the changes in Linux kernel (see https://lkml.org/lkml/2018/3/1/268 ) Note: This will add support only for the limited use case of register ... asm("rN"). Any other uses that make rN leak into assembly are not supported. Reviewers: kristof.beyls, rengolin, peter.smith, t.p.northover Reviewed By: peter.smith Subscribers: javed.absar, eraman, cfe-commits, srhines Differential Revision: https://reviews.llvm.org/D44815 llvm-svn: 328829
* [ARM] Pass half or i16 types for NEON intrinsicsSjoerd Meijer2018-03-191-0/+2
| | | | | | | | | | | | | | | For generating NEON intrinsics, this determines the NEON data type, and whether it should be a half type or an i16 type. I.e., we always pass a half type for AArch64, this hasn't changed, but now also for ARM but only when FullFP16 is enabled, and i16 otherwise. This is intended to be non-functional change, but together with the backend work in D44538 which adds support for f16 vectors, this enables adding the AArch32 FP16 (vector) intrinsics. Differential Revision: https://reviews.llvm.org/D44561 llvm-svn: 327836
* Make march/target-cpu print a note with the list of valid values for ARMErich Keane2018-02-081-0/+5
| | | | | | | | | | | | When rejecting a march= or target-cpu command line parameter, the message is quite lacking. This patch adds a note that prints all possible values for the current target, if the target supports it. This adds support for the ARM/AArch64 targets (more to come!). Differential Revision: https://reviews.llvm.org/D42978 llvm-svn: 324673
* [AArch64] Add ARMv8.2-A FP16 scalar intrinsicsAbderrazek Zaafrani2018-01-191-0/+2
| | | | | | https://reviews.llvm.org/D41792 llvm-svn: 323006
* Avoid int to string conversion in Twine or raw_ostream contexts.Benjamin Kramer2017-12-281-1/+1
| | | | | | Some output changes from uppercase hex to lowercase hex, no other functionality change intended. llvm-svn: 321526
* [AARch64] Add ARMv8.2-A FP16 vector intrinsicsAbderrazek Zaafrani2017-12-211-0/+3
| | | | | | | | Putting back the code that was reverted few weeks ago. Differential Revision: https://reviews.llvm.org/D34161 llvm-svn: 321294
* [MINGW] normalize WIN32 macrosMartell Malone2017-11-211-13/+0
| | | | | | | | | | | | | | move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h move WIN32, WIN64 and __MINGW64__ to addMinGWDefines fixes __MINGW64__ not being defined for aarch64 adds WIN32 definition for x64 Reviewers: mstorsjo Differential Revision: https://reviews.llvm.org/D40285 llvm-svn: 318755
* [COFF, ARM64] Add MS builtins __dmb, __dsb, __isbMartin Storsjo2017-10-121-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D38821 llvm-svn: 315567
* Driver: hoist the `wchar_t` handling to the driverSaleem Abdulrasool2017-10-061-6/+7
| | | | | | | | | | | | | | | | Move the logic for determining the `wchar_t` type information into the driver. Rather than passing the single bit of information of `-fshort-wchar` indicate to the frontend the desired type of `wchar_t` through a new `-cc1` option of `-fwchar-type` and indicate the signedness through `-f{,no-}signed-wchar`. This replicates the current logic which was spread throughout Basic into the `RenderCharacterOptions`. Most of the changes to the tests are to ensure that the frontend uses the correct type. Add a new test set under `test/Driver/wchar_t.c` to ensure that we calculate the proper types for the various cases. llvm-svn: 315126
* Basic: support Preserve{Most,All} CC on WindowsSaleem Abdulrasool2017-09-261-0/+2
| | | | | | | Add support for the `preserve_mostcc` and `preserve_allcc` on Windows x86_64 and AArch64. This is used by Swift. llvm-svn: 314236
* [AArch64] Add support for a MinGW AArch64 targetMartin Storsjo2017-08-131-21/+42
| | | | | | Differential Revision: https://reviews.llvm.org/D36364 llvm-svn: 310798
* [AArch64] Ignore stdcall and similar on aarch64/windowsMartin Storsjo2017-08-071-0/+17
| | | | | | | | | | This is similar to what's done on arm and x86_64, where these calling conventions are silently ignored, as in SVN r245076. Differential Revision: https://reviews.llvm.org/D36105 llvm-svn: 310303
* [AArch64] Don't define __LP64__ when targeting WindowsMartin Storsjo2017-07-311-2/+4
| | | | | | | | | Windows/ARM64 is a LLP64 environment, so don't set this default define. Differential Revision: https://reviews.llvm.org/D36098 llvm-svn: 309619
* Update to use enum classes for various ARM *Kind enumsFlorian Hahn2017-07-271-7/+6
| | | | | | | | | | | | | | Summary: This updates the relevant Clang parts for the LLVM change D35882. Reviewers: rengolin, chandlerc, javed.absar, rovka Reviewed By: rovka Subscribers: aemerson, cfe-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D35884 llvm-svn: 309289
* AArch64 & ARM: move TargetInfo functions from .h to .cpp file. NFC.Tim Northover2017-07-241-8/+443
| | | | | | | Most of them are virtual anyway, and the few remaining ones can move to the .cpp for consistency. llvm-svn: 308898
* Break up Targets.cpp into a header/impl pair per target type[NFCI]Erich Keane2017-07-211-0/+71
Targets.cpp is getting unwieldy, and even minor changes cause the entire thing to cause recompilation for everyone. This patch bites the bullet and breaks it up into a number of files. I tended to keep function definitions in the class declaration unless it caused additional includes to be necessary. In those cases, I pulled it over into the .cpp file. Content is copy/paste for the most part, besides includes/format/etc. Differential Revision: https://reviews.llvm.org/D35701 llvm-svn: 308791
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