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* Basic: fix __USER_LABEL_PREFIX__ on CygwinSaleem Abdulrasool2016-02-261-0/+1
| | | | | | | | Adjust the user label prefix for cygwin x86_64. Resolves PR26744. llvm-svn: 262030
* Added SKL and CNL processors and features to ClangElena Demikhovsky2016-02-211-14/+81
| | | | | | Differential Revision: http://reviews.llvm.org/D16756 llvm-svn: 261467
* ARM: fix VFP asm constraintsJF Bastien2016-02-191-2/+2
| | | | | | | | | | | | | | | Summary: Rich Felker was sad that clang used 'w' and 'P' for VFP constraints when GCC documents them as 't' and 'w': https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html This was added way back in 2008: http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20080421/005393.html Subscribers: aemerson, rengolin, cfe-commits Differential Revision: http://reviews.llvm.org/D17349 llvm-svn: 261309
* [Hexagon] Specify vector alignment in DataLayout stringKrzysztof Parzyszek2016-02-121-3/+6
| | | | | | | | | | | The DataLayout can calculate alignment of vectors based on the alignment of the element type and the number of elements. In fact, it is the product of these two values. The problem is that for vectors of N x i1, this will return the alignment of N bytes, since the alignment of i1 is 8 bits. The vector types of vNi1 should be aligned to N bits instead. Provide explicit alignment for HVX vectors to avoid such complications. llvm-svn: 260680
* [Driver] Add support for Qualcomm's Kryo CPU.Chad Rosier2016-02-111-0/+1
| | | | | | http://reviews.llvm.org/D17124 llvm-svn: 260555
* [ARM] Add command-line options for ARMv8.2-AOliver Stannard2016-02-111-0/+2
| | | | | | | | | | | | | | | | | This allows ARMv8.2-A to be targeted either by using "armv8.2a" in the triple, or by using -march=armv8.2-a (or the alias -march=armv8.2a). The FP16 extension can be enabled with the "+fp16" suffix to the -march or -mcpu option. This is consistent with the AArch64 option, rather than the usual ARM option of -mfpu. We have agreed with the team which will be upstreaming this to GCC that we want to use this new option format for new architecture extensions for both ARM and AArch64. Most of the work for this was done by the TargetParser patch in llvm. Differential Revision: http://reviews.llvm.org/D15040 llvm-svn: 260533
* Reapply the patch of r260376.Andrey Turetskiy2016-02-101-2/+2
| | | | llvm-svn: 260379
* [X86] Fix stack alignment for MCU target (Clang part), by Anton Nadolskiy.Andrey Turetskiy2016-02-101-0/+9
| | | | | | | | This patch fixes stack alignments for MCU (should be aligned to 4 bytes). Differential Revision: http://reviews.llvm.org/D15647 llvm-svn: 260376
* [SystemZ] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macrosUlrich Weigand2016-02-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_[1248] macros on SystemZ. This fixes a miscompile of GCC C++11 standard library headers due to use of those macros in an ABI-changing manner. See e.g. /usr/include/c++/4.8.5/ext/concurrence.h: // Compile time constant that indicates prefered locking policy in // the current configuration. static const _Lock_policy __default_lock_policy = #ifdef __GTHREADS #if (defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) \ && defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4)) _S_atomic; #else _S_mutex; #endif #else _S_single; #endif A different choice of __default_lock_policy causes different sizes of several of the C++11 data structures, which are then incompatible when inlined in clang-compiled code with what the (GCC-compiled) external library expects. This in turn leads to various crashes when using std::thread in code compiled with clang, as see e.g. via the ThreadPool unit tests. See PR 26473 for an example. llvm-svn: 259931
* Do not honor explicit alignment attribute on fields for PS4.Sunil Srivastava2016-02-051-0/+4
| | | | | | | | This change reverts r257462 for PS4 triple. Differential Revision: http://reviews.llvm.org/D16788 llvm-svn: 259916
* [x86] Correct setting of WIntType for MCU targetAndrey Bokhanko2016-02-041-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D16626 llvm-svn: 259780
* Basic: mark TLS as supported on Windows on ARMSaleem Abdulrasool2016-02-041-1/+0
| | | | | | | LLVM can now lower TLS access as per the MS ABI on ARM. This enables the generation of TLS access for Windows on ARM. llvm-svn: 259751
* -inline-asm][X86] Add ability to use AVX512 in MS inline asmMarina Yatsina2016-02-031-0/+8
| | | | | | | | | Defined the new AVX512 registers in clang inline asm. Fixed a bug in the MC subtarget info creation during the parsing of MS asm statement - now it receives the actual CPU and target features information. Differential Revision: http://reviews.llvm.org/D16757 llvm-svn: 259639
* Fix attribute((mode([word|unwind_word]))) for x32Reid Kleckner2016-02-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by H.J. Lu ``` typedef unsigned int gcc_word __attribute__((mode(word))); ``` and ``` typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word))); ``` define the largest unsigned integer types which can be stored in a general purpose register, which may not be the pointer type. For x32, they aren't pointer nor unsigned long. We should 1. Make getUnwindWordWidth and getRegisterWidth virtual, 2. Override them for x32, similar to hasInt128Type. 3. Use getRegisterWidth for __attribute__((mode(word))); This fixes PR 24706. Reviewers: rnk Differential Revision: http://reviews.llvm.org/D16779 llvm-svn: 259383
* ARMv7k: select ABI based on v7k Arch rather than watchos OS.Tim Northover2016-01-271-5/+5
| | | | | | | | Various bits we'd like to use the new ABI actually compile with "-arch armv7k -miphoneos-version-min=9.0". Not ideal, but also not ridiculous given how slices work. llvm-svn: 258976
* Revert "Change of UserLabelPrefix default value from "_" to """James Y Knight2016-01-271-22/+31
| | | | | | | | | | | | | This reverts commit r258504. This commit breaks (at least) sparc-rtems -- the OS (RTEMS) used to override UserLabelPrefix to "", despite the arch (SPARC) having set it to "_". Now, the OS doesn't override anymore, but the arch sets it to "_", resulting in the wrong value. I expect this probably breaks other OSes that overrode to "" before, as well. (Clearly we have some missing test cases, here...) llvm-svn: 258894
* Change of UserLabelPrefix default value from "_" to ""Andrey Bokhanko2016-01-221-31/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D16295 llvm-svn: 258504
* Correct setting of UserLabelPrefix for MCU target.Andrey Bokhanko2016-01-141-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D16138 llvm-svn: 257756
* ARM: allow __thread on OS versions that have the required runtime support.Tim Northover2016-01-071-1/+18
| | | | llvm-svn: 257041
* [WebAssembly] Add -m:e to the target triple.Dan Gohman2016-01-071-2/+2
| | | | llvm-svn: 257021
* [AArch64] Teaches clang about Samsung Exynos-M1MinSeong Kim2016-01-051-1/+2
| | | | | | | | Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15664 llvm-svn: 256829
* [X86][PKU] add clang intrinsic for {RD|WR}PKRUAsaf Badouh2015-12-311-1/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D15837 llvm-svn: 256672
* Replace llvm::utostr calls in Twine context with Twines. NFC.Benjamin Kramer2015-12-241-1/+1
| | | | llvm-svn: 256377
* [mips] Add _GCC_HAVE_SYNC_COMPARE_AND_SWAP macros.Daniel Sanders2015-12-221-0/+8
| | | | | | | This fixes the 'pure virtual function called' failure with ThreadPool in a clang-built clang. This fixes the llvm-mips-linux builder. llvm-svn: 256240
* [Cygwin] Enable TLS as emutls.NAKAMURA Takumi2015-12-211-1/+0
| | | | | | | | It resolves clang selfhosting with std::once() for Cygwin. FIXME: It may be EmulatedTLS-generic also for X86-Android. FIXME: Pass EmulatedTLS to LLVM CodeGen from Clang with -femulated-tls. llvm-svn: 256134
* [Hexagon] Update default paths and argumentsKrzysztof Parzyszek2015-12-141-41/+72
| | | | | | | | | - Removed support for hexagonv3 and earlier. - Added handling of hexagonv55 and hexagonv60. - Added handling of target features (hvx, hvx-double). - Updated paths to reflect current directory layout. llvm-svn: 255502
* [WebAssembly] Remove an obsolete TODO comment.Dan Gohman2015-12-051-1/+0
| | | | llvm-svn: 254817
* Teaches clang about Cortex-A35.Christof Douma2015-12-021-1/+1
| | | | | | | | Adds support for the new Cortex-A35 ARMv8-A core. Differential Revision: http://reviews.llvm.org/D15142 llvm-svn: 254505
* ARM v8.1a adds Advanced SIMD instructions for Rounding Double MultiplyAlexandros Lamprineas2015-11-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Add/Subtract. The following instructions are added to AArch32 instruction set: - VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half - VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half The following instructions are added to AArch64 instruction set: - SQRDMLAH: Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half - SQRDMLSH: Signed Saturating Rounding Doubling Multiply Subtract Returning High Half This patch adds intrinsic and ACLE macro support for these instructions, as well as corresponding tests. Differential Revision: http://reviews.llvm.org/D14982 llvm-svn: 254250
* [X86] Support for C calling convention only for MCU target.Alexey Bataev2015-11-251-10/+23
| | | | | | | For MCU only C calling convention is allowed, all other calling conventions are not supported. Differential Revision: http://reviews.llvm.org/D14864 llvm-svn: 254063
* AMDGPU: Add support for 's' and 'v' asm constraintsTom Stellard2015-11-191-2/+9
| | | | | | | | | | | | Summary: 's' is used to specify sgprs and 'v' is used to specify vgprs. Reviewers: arsenm, echristo Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D14307 llvm-svn: 253610
* Produce a better diagnostic for global register variables.Akira Hatanaka2015-11-181-0/+30
| | | | | | | | | | | | | | | | | | Currently, when there is a global register variable in a program that is bound to an invalid register, clang/llvm prints an error message that is not very user-friendly. This commit improves the diagnostic and moves the check that used to be in the backend to Sema. In addition, it makes changes to error out if the size of the register doesn't match the declared variable size. e.g., volatile register int B asm ("rbp"); rdar://problem/23084219 Differential Revision: http://reviews.llvm.org/D13834 llvm-svn: 253405
* [ARM] Pass in the architecture to TargetParser to cope with API changeBradley Smith2015-11-161-2/+3
| | | | | | | | The TargetParser API to get the default FPU and default extensions has changed so that it can fall back to the architecture in case of a generic CPU. llvm-svn: 253199
* Cull non-standard variants of ARM architectures (NFC)Artyom Skrobov2015-11-121-5/+0
| | | | | | | | | | | | Summary: Clang-side update, corresponding to D14577 Reviewers: rengolin Subscribers: aemerson, cfe-commits, rengolin Differential Revision: http://reviews.llvm.org/D14578 llvm-svn: 252904
* Silencing a -Wreturn-type warning for control reaching the end of a non-void ↵Aaron Ballman2015-11-111-0/+1
| | | | | | function. llvm-svn: 252727
* [WebAssembly] Change long double to be quadruple-precision floating point.Dan Gohman2015-11-101-0/+2
| | | | llvm-svn: 252646
* Add the variant of __sparc_v9__ with five underscores, not just four.Joerg Sonnenberger2015-11-101-1/+3
| | | | llvm-svn: 252640
* Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8Joerg Sonnenberger2015-11-091-14/+88
| | | | | | | | | is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
* [x86] Additional small fix for MCU psABI supportAndrey Bokhanko2015-11-051-2/+6
| | | | | | | | This patch fixes one more thing in MCU psABI support: LongDoubleWidth should be set to 64. Differential Revision: http://reviews.llvm.org/D14285 llvm-svn: 252156
* [x86] Front-end part of MCU psABI supportAndrey Bokhanko2015-11-021-1/+7
| | | | | | | | | | | This patch implements two things in front-end for MCU psABI support: 1) "long double type is the same as double." 2) "New predefined C/C++ pre-processor symbols: iamcu and iamcu__. Differential Revision: http://reviews.llvm.org/D14205 llvm-svn: 251786
* ARMv7k: implement ABI changes for watchOS from standard iOS.Tim Northover2015-10-301-10/+40
| | | | llvm-svn: 251710
* Watch and TV OS: wire up basic ABI choicesTim Northover2015-10-301-1/+4
| | | | | | | This sets the mostly expected Darwin default ABI options for these two platforms. Active changes from these defaults for watchOS are in a later patch. llvm-svn: 251708
* Preprocessor: define correct tvOS and watchOS version macrosTim Northover2015-10-301-1/+16
| | | | llvm-svn: 251707
* Fix the calling convention of Mingw64 long double valuesReid Kleckner2015-10-281-1/+7
| | | | | | | | | | GCC uses the x87DoubleExtended model for long doubles, and passes them indirectly by address through function calls. Also replace the existing mingw-long-double assembly emitting test with an IR-level test. llvm-svn: 251567
* Simplify boolean conditional return statements in lib/Basic.Rafael Espindola2015-10-241-3/+3
| | | | | | Patch by Richard. llvm-svn: 251214
* [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-devArtyom Skrobov2015-10-231-1/+1
| | | | llvm-svn: 251124
* Define weak and __weak to mean ARC-style weak references, even in MRC.John McCall2015-10-221-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, __weak was silently accepted and ignored in MRC mode. That makes this a potentially source-breaking change that we have to roll out cautiously. Accordingly, for the time being, actual support for __weak references in MRC is experimental, and the compiler will reject attempts to actually form such references. The intent is to eventually enable the feature by default in all non-GC modes. (It is, of course, incompatible with ObjC GC's interpretation of __weak.) If you like, you can enable this feature with -Xclang -fobjc-weak but like any -Xclang option, this option may be removed at any point, e.g. if/when it is eventually enabled by default. This patch also enables the use of the ARC __unsafe_unretained qualifier in MRC. Unlike __weak, this is being enabled immediately. Since variables are essentially __unsafe_unretained by default in MRC, the only practical uses are (1) communication and (2) changing the default behavior of by-value block capture. As an implementation matter, this means that the ObjC ownership qualifiers may appear in any ObjC language mode, and so this patch removes a number of checks for getLangOpts().ObjCAutoRefCount that were guarding the processing of these qualifiers. I don't expect this to be a significant drain on performance; it may even be faster to just check for these qualifiers directly on a type (since it's probably in a register anyway) than to do N dependent loads to grab the LangOptions. rdar://9674298 llvm-svn: 251041
* Fix __ARM_FP value for sp-only FPUs with Half-precisionRichard Barton2015-10-211-1/+1
| | | | | | | | | The logic for parsing FP capabilities to set __ARM_FP was mistakenly removing the Half-Precision capability when handling fp-only-sp resulting in a value of 0x4. Section 6.5.1 of ACLE states that for such FP architectures the value should be 0x6 llvm-svn: 250888
* [X86] Remove a few 'else' after 'return'Craig Topper2015-10-201-7/+6
| | | | llvm-svn: 250764
* Make getTargetBuiltins return an ArrayRef instead of having two out ↵Craig Topper2015-10-191-63/+44
| | | | | | parameters of a pointer and length. NFC llvm-svn: 250681
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