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* [AArch64] Change the preferred alignment for char and short to word alignmentEvandro Menezes2016-06-211-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D21414 llvm-svn: 273280
* NVPTX: Add supported CL featuresJan Vesely2016-06-171-0/+13
| | | | | | | | | | Fixes libclc compilation broken by r269670 Reviewers: jholewinsky Differential Revision: http://reviews.llvm.org/D20389 llvm-svn: 273031
* AMDGPU: Fix supported CL featuresJan Vesely2016-06-171-23/+22
| | | | | | | | Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D20388 llvm-svn: 272986
* [Sparc] setjmp and longjmp intrinsic support update to add unit tests and ↵Chris Dewhurst2016-06-151-1/+0
| | | | | | | | remove accidentally checked-in code. Related to revision r272782 llvm-svn: 272798
* [Sparc] Change to let clang know that setjmp and longjmp intrinsics are ↵Chris Dewhurst2016-06-151-0/+5
| | | | | | | | implemented in the back-end. Differential Revision: http://reviews.llvm.org/D19798 llvm-svn: 272782
* [mips] Defer validity check for CPU/ABI pairs and improve error message for ↵Daniel Sanders2016-06-141-34/+79
| | | | | | | | | | | | | | | | | | | | | invalid cases. Summary: The validity of ABI/CPU pairs is no longer checked on the fly but is instead checked after initialization. As a result, invalid CPU/ABI pairs can be reported as being known but invalid instead of being unknown. For example, we now emit: error: ABI 'n32' is not supported on CPU 'mips32r2' instead of: error: unknown target ABI 'n64' Reviewers: atanasyan Subscribers: sdardis, cfe-commits Differential Revision: http://reviews.llvm.org/D21023 llvm-svn: 272645
* AMDGPU: Verify subtarget specific builtinsMatt Arsenault2016-06-081-49/+87
| | | | | | Cleanup setup of subtarget features. llvm-svn: 272091
* [mips] The P5600 does not support N32/N64 since it's a 32-bit CPU.Daniel Sanders2016-06-061-1/+1
| | | | | | | | | | | | Summary: Reviewers: atanasyan Subscribers: cfe-commits, sdardis Differential Revision: http://reviews.llvm.org/D20963 llvm-svn: 271877
* [mips] Replace almost all Arch checks in MipsTargetInfo with ABI checks. NFC.Daniel Sanders2016-06-061-51/+65
| | | | | | | | | | | | | | Summary: setABI() is still tied to the Arch component of the Triple to preserve existing behaviour. Reviewers: atanasyan Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D20961 llvm-svn: 271875
* [mips] Slightly simplify MipsTargetInfo::setDataLayout(). NFC.Daniel Sanders2016-06-031-19/+15
| | | | | | | | | | | | Summary: Reviewers: atanasyan Subscribers: atanasyan, cfe-commits Differential Revision: http://reviews.llvm.org/D20680 llvm-svn: 271647
* This adds target support and tests for Cortex-A73Sjoerd Meijer2016-06-021-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D20864 llvm-svn: 271507
* AMDGPU: Update datalayout stringMatt Arsenault2016-05-311-1/+1
| | | | llvm-svn: 271297
* [mips] Kill 'support' for untested EABI.Daniel Sanders2016-05-271-6/+4
| | | | | | | | | | | | | | | | | Summary: There are no llvm backend tests* for EABI and no EABI buildbots. There were only three clang tests, all of which checked that -mabi=eabi was passed to the assembler. *There is a single backend test that specifies EABI but it actually tests MIPS16. Reviewers: atanasyan Subscribers: emaste, sdardis, atanasyan, cfe-commits Differential Revision: http://reviews.llvm.org/D20679 llvm-svn: 270998
* [mips] Fold MipsTargetInfoBase subclasses into MipsTargetInfoBase and rename ↵Daniel Sanders2016-05-271-317/+209
| | | | | | | | | | | | | | | | | to MipsTargetInfo. NFC Summary: This unifies mips/mipsel and mips64/mips64el into a single class so that we can later support O32 on mips64/mips64el and N32/N64 on mips/mipsel (when an appropriate CPU selected). Reviewers: atanasyan Subscribers: atanasyan, jfb, cfe-commits, dschuff Differential Revision: http://reviews.llvm.org/D20678 llvm-svn: 270984
* Revert "[AArch64] Using new TargetParser in Clang"Renato Golin2016-05-251-4/+8
| | | | | | | | This reverts commit r270688 and r270689. The issue is not a random order, but a different order for some targets and others (prob. Linux vs Darwin). Reverting until we have a better fix. llvm-svn: 270691
* [AArch64] Using new TargetParser in ClangRenato Golin2016-05-251-8/+4
| | | | | | | | | | Using AArch64TargetParser in clang to avoid repetitive string parsing. Use TargetParser to do ARCH/CPU/ArchExt parsing instead of local implementation. Patch by Jojo Ma. llvm-svn: 270688
* [Sparc] Add software float option -msoft-floatJacob Baungard Hansen2016-05-241-3/+1
| | | | | | | | | | | | | | | Summary: Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option. The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided. Reviewers: jyknight, lero_chris Subscribers: jyknight, cfe-commits Differential Revision: http://reviews.llvm.org/D20419 llvm-svn: 270538
* Make __FreeBSD_cc_version predefined macro configurable at build timeDimitry Andric2016-05-201-2/+9
| | | | | | | | | | | | | | | | | | The `FreeBSDTargetInfo` class has always set the `__FreeBSD_cc_version` predefined macro to a rather static value, calculated from the major OS version. In the FreeBSD base system, we will start incrementing the value of this macro whenever we make any signifant change to clang, so we need a way to configure the macro's value at build time. Use `FREEBSD_CC_VERSION` for this, which we can define in the FreeBSD build system using either the `-D` command line option, or an include file. Stock builds will keep the earlier value. Differential Revision: http://reviews.llvm.org/D20037 llvm-svn: 270240
* Add all the avx512 flavors to __builtin_cpu_supports's list.Benjamin Kramer2016-05-201-0/+11
| | | | | | | | This is matching what trunk gcc is accepting. Also adds a missing ssse3 case. PR27779. The amount of duplication here is annoying, maybe it should be factored into a separate .def file? llvm-svn: 270224
* [Hexagon] Recognize "s" constraint in inline-asmKrzysztof Parzyszek2016-05-201-0/+3
| | | | llvm-svn: 270216
* [CUDA] Allow sm_50,52,53 GPUsArtem Belevich2016-05-191-0/+15
| | | | | | | | LLVM accepts them since r233575. Differential Revision: http://reviews.llvm.org/D20405 llvm-svn: 270084
* [Hexagon] Recognize "q" and "v" in inline-asm as register constraintsKrzysztof Parzyszek2016-05-181-1/+10
| | | | | | Clang follow-up to r269933. llvm-svn: 269934
* Add new intrinsic support for MONITORX and MWAITX instructionsAshutosh Nema2016-05-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits Differential Revision: http://reviews.llvm.org/D19796 llvm-svn: 269907
* [PS4] Change the names of some "environmental" things to what ourPaul Robinson2016-05-161-1/+1
| | | | | | | | licensees actually see in the toolchain we deliver to them. This will reduce the set of local patches we have to maintain. The triple is not changing. (The term ORBIS is an internal code name for PS4.) llvm-svn: 269671
* [OpenCL] Add supported OpenCL extensions to target info.Yaxun Liu2016-05-161-11/+37
| | | | | | | | | | Add supported OpenCL extensions to target info. It serves as default values to save the users of the burden setting each supported extensions and optional core features in command line. Re-commit after fixing build error due to missing override attribute. Differential Revision: http://reviews.llvm.org/D19484 llvm-svn: 269670
* ARM-MachO: stop claiming to be EABITim Northover2016-05-131-1/+1
| | | | | | | | | | Embedded ARM MachO targets are AAPCS but not full EABI (we don't use __aeabi_whatever and the functions are allowed to be hard-float). Turns out there was already a test for this, but its original purpose had become corrupted over the years. llvm-svn: 269487
* Revert "[OpenCL] Add supported OpenCL extensions to target info."Yaxun Liu2016-05-131-37/+11
| | | | | | | | | Revert r269431 due to build failure caused by warning msg: llvm/tools/clang/lib/Basic/Targets.cpp:2090:9: error: 'setSupportedOpenCLOpts' overrides a member function but is not marked 'override' [-Werror,-Winconsistent-missing-override] void setSupportedOpenCLOpts() { llvm-svn: 269435
* [OpenCL] Add supported OpenCL extensions to target info.Yaxun Liu2016-05-131-11/+37
| | | | | | | | Add supported OpenCL extensions to target info. It serves as default values to save the users of the burden setting each supported extensions and optional core features in command line. Differential Revision: http://reviews.llvm.org/D19484 llvm-svn: 269431
* Update clang support on recent HaikuReid Kleckner2016-05-111-9/+28
| | | | | | | | | | | | | | | | | | [ Copied from https://llvm.org/bugs/show_bug.cgi?id=26404 ] clang support on Haiku is lagging a bit, and missing on x86_64. This patch updates support for x86 and add support for x86_64. It should apply directly to trunk and it's harmless in the sense that it only affects Haiku. Reviewers: rnk, rsmith Patch by Jérôme Duval Differential Revision: http://reviews.llvm.org/D16797 llvm-svn: 269201
* [Power9] Enable -mcpu=pwr9 (-mcpu=power9) in the front endNemanja Ivanovic2016-05-091-2/+22
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D19684 It simply adds the handling for the option and the corresponding macros. llvm-svn: 268951
* Enable support for __float128 in Clang and enable it on pertinent platformsNemanja Ivanovic2016-05-091-4/+23
| | | | | | | | | | | | | | | | | | This patch corresponds to reviews: http://reviews.llvm.org/D15120 http://reviews.llvm.org/D19125 It adds support for the __float128 keyword, literals and target feature to enable it. Based on the latter of the two aforementioned reviews, this feature is enabled on Linux on i386/X86 as well as SystemZ. This is also the second attempt in commiting this feature. The first attempt did not enable it on required platforms which caused failures when compiling type_traits with -std=gnu++11. If you see failures with compiling this header on your platform after this commit, it is likely that your platform needs to have this feature enabled. llvm-svn: 268898
* [Sparc] Implement __builtin_setjmp, __builtin_longjmp back-end.Chris Dewhurst2016-05-041-0/+4
| | | | | | | | | | | | | | This code implements builtin_setjmp and builtin_longjmp exception handling intrinsics for 32-bit Sparc back-ends. The code started as a mash-up of the PowerPC and X86 versions, although there are sufficient differences to both that had to be made for Sparc handling. Note: I have manual tests running. I'll work on a unit test and add that to the rest of this diff in the next day. Also, this implementation is only for 32-bit Sparc. I haven't focussed on a 64-bit version, although I have left the code in a prepared state for implementing this, including detecting pointer size and comments indicating where I suspect there may be differences. Differential Revision: http://reviews.llvm.org/D19798 llvm-svn: 268483
* [CUDA] Copy host builtin types to NVPTXTargetInfo.Justin Lebar2016-04-291-1/+63
| | | | | | | | | | | | | | | | | Summary: Host and device types must match, otherwise when we pass values back and forth between the host and device, we will get the wrong result. This patch makes NVPTXTargetInfo inherit most of its type information from the host's target info. Reviewers: rsmith Subscribers: cfe-commits, jhen, tra Differential Revision: http://reviews.llvm.org/D19346 llvm-svn: 268131
* [Clang][Darwin] Define __ARM_DWARF_EH__ for WatchABIChris Bieneman2016-04-291-0/+4
| | | | | | | | | | | | Summary: The Darwin armv7k ABI uses Dwarf EH, so we need to set the OS define correctly. Without this the gcc_personality fails to build. Reviewers: t.p.northover Subscribers: aemerson, cfe-commits, rengolin Differential Revision: http://reviews.llvm.org/D19693 llvm-svn: 268078
* ARMv7k: define __ARM_PCS_VFP since we're hard-float.Tim Northover2016-04-281-3/+4
| | | | | | | | It's a little debateable because we're not truly AAPCS, so I'm certainly not going to define __ARM_PCS, but __ARM_PCS_VFP seems to be really an "hard-float" define, which is a useful thing to have. llvm-svn: 267880
* [SystemZ] Support Swift calling conventionBryan Chan2016-04-281-0/+10
| | | | | | | | | | | | | | | Summary: Port rL265324 to SystemZ to allow using the 'swiftcall' attribute on that architecture. Depends on D19414. Reviewers: kbarton, rjmccall, uweigand Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D19432 llvm-svn: 267879
* PR27216: Only define __ARM_FEATURE_FMA when the target has VFPv4Silviu Baranga2016-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: According to the ACLE spec, "__ARM_FEATURE_FMA is defined to 1 if the hardware floating-point architecture supports fused floating-point multiply-accumulate". This changes clang's behaviour from emitting this macro for v7-A and v7-R cores to only emitting it when the target has VFPv4 (and therefore support for the floating point multiply-accumulate instruction). Fixes PR27216 Reviewers: t.p.northover, rengolin Subscribers: aemerson, rengolin, cfe-commits Differential Revision: http://reviews.llvm.org/D18963 llvm-svn: 267869
* [Hexagon] Define architecture version macros for hexagonv55Krzysztof Parzyszek2016-04-211-0/+5
| | | | llvm-svn: 266989
* [Hexagon] Define macros __HVX__ and __HVXDBL__ when appropriateKrzysztof Parzyszek2016-04-181-0/+6
| | | | llvm-svn: 266647
* [ARM] predefines __ELF__ macro for arm-none-eabiWeiming Zhao2016-04-181-0/+4
| | | | | | | | | | | | Summary: predefines __ELF__ macro for arm-none-eabi Reviewers: silviu.baranga, rengolin Subscribers: aemerson, rengolin, cfe-commits Differential Revision: http://reviews.llvm.org/D19225 llvm-svn: 266625
* Revert 266186 as it breaks anything that includes type_traits on some platformsNemanja Ivanovic2016-04-151-21/+5
| | | | | | | | | | Since this patch provided support for the __float128 type but disabled it on all platforms by default, some platforms can't compile type_traits with -std=gnu++11 since there is a specialization with __float128. This reverts the patch until D19125 is approved (i.e. we know which platforms need this support enabled). llvm-svn: 266460
* Enable support for __float128 in ClangNemanja Ivanovic2016-04-131-5/+21
| | | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D15120 It adds support for the __float128 keyword, literals and a target feature to enable it. This support is disabled by default on all targets and any target that has support for this type is free to add it. Based on feedback that I've received from target maintainers, this appears to be the right thing for most targets. I have not heard from the maintainers of X86 which I believe supports this type. I will subsequently investigate the impact of enabling this on X86. llvm-svn: 266186
* Basic: fix profiling with GNU EABISaleem Abdulrasool2016-04-121-0/+4
| | | | | | | | | The GNU profiling support indicates that the interface is `_mcount` rather than `mcount`. Conditionalise the behaviour according to the `-meabi gnu` flag. Resolves PR27311 llvm-svn: 266039
* Correct pg instrumentation for AArch64Saleem Abdulrasool2016-04-101-5/+0
| | | | | | | | | It seems that there was a miscommunication between Renato and I, and the original behaviour of AArch64 was to be preserved and not to mirror the new behaviour. Restore the original behaviour for AArch64. Addresses post-commit review comments from Renato Golin. llvm-svn: 265899
* Add support for __gnu_mcount_nc as the pg interfaceSaleem Abdulrasool2016-04-101-2/+11
| | | | | | | | | | | This adds support to optionally support using `__gnu_mcount_nc` as the mcount interface rather than `mcount` for Linux and EABI. The other targets do not provide an implementation for `__gnu_mcount_nc`. This can be activated via the `-meabi gnu` flag. Resolves PR23969. llvm-svn: 265888
* Basic: thread TargetOptions into TargetInfoSaleem Abdulrasool2016-04-091-292/+335
| | | | | | | | This threads TargetOptions into the TargetInfo hierarchy. This is a rework of the original attempt to thread additional information into the TargetInfo to make decisions based on additional ABI related options. llvm-svn: 265878
* revert SVN r265702, r265640Saleem Abdulrasool2016-04-081-358/+293
| | | | | | | | | | | Revert the two changes to thread CodeGenOptions into the TargetInfo allocation and to fix the layering violation by moving CodeGenOptions into Basic. Code Generation is arguably not particularly "basic". This addresses Richard's post-commit review comments. This change purely does the mechanical revert and will be followed up with an alternate approach to thread the desired information into TargetInfo. llvm-svn: 265806
* Basic: move CodeGenOptions from FrontendSaleem Abdulrasool2016-04-071-2/+2
| | | | | | | | This is a mechanical move of CodeGenOptions from libFrontend to libBasic. This fixes the layering violation introduced earlier by threading CodeGenOptions into TargetInfo. It should also fix the modules based self-hosting builds. NFC. llvm-svn: 265702
* Basic: thread CodeGenOptions into TargetInfoSaleem Abdulrasool2016-04-071-292/+357
| | | | | | | | | This threads CodeGenOptions into the TargetInfo hierarchy. This is motivated by ARM which can change some target information based on the EABI selected (-meabi). Similar options exist for other platforms (e.g. MIPS) and thus is generally useful. NFC. llvm-svn: 265640
* [X86] Introduction of -march=lakemont.Andrey Turetskiy2016-04-051-3/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D18651 llvm-svn: 265405
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