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* [Reassociate] regenerate checks; NFCSanjay Patel2018-03-011-61/+62
| | | | llvm-svn: 326511
* revert r326502: [InstCombine] allow fmul fold with less than 'fast'Sanjay Patel2018-03-012-14/+12
| | | | | | | | I forgot that I added tests for 'reassoc' to -reassociate, but suprisingly that file calls -instcombine too, so it is affected. I'll update that file and try again. llvm-svn: 326510
* [WebAssembly] Simplify COMDAT handling.Rui Ueyama2018-03-013-22/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D43966 llvm-svn: 326509
* Revert r326501 due to buildbot breakage.David L. Jones2018-03-016-25/+35
| | | | | | | | | | | | | | | | | | | | Original change: [NFC] Move CommentOpts checks to the call sites that depend on it. When parsing comments, for example, for -Wdocumentation, slightly different behaviour occurs when -fparse-all-comments is specified. However, these differences are subtle: 1. All comments are saved during parsing, regardless of whether they are doc comments or not. 2. "Maybe-doc" comments, like //<, //!, etc, are saved as such, instead of marking them as ordinary comments. The maybe-doc type of comment is never saved otherwise. (Warning on these is the impetus of -Wdocumentation.) 3. All comments are treated as doc comments in ASTContext, even if they are ordinary. This change moves the logic for checking CommentOptions.ParseAllComments closer to where it has an effect. The overall logic is unchanged, but checks of the ParseAllComments flag are now done where the effect will be clearer. llvm-svn: 326508
* Report an error if you try to link against .dll instead of .lib.Rui Ueyama2018-03-012-11/+23
| | | | | | | | | | | | It is a usage error to feed a .dll file instead of a .dll to COFF linker. Previously, lld failed with a mysterious error message. Now we reject it at the driver. Fixes https://bugs.llvm.org/show_bug.cgi?id=36440 Differential Revision: https://reviews.llvm.org/D43964 llvm-svn: 326507
* Accept both `--foo bar` and `--foo=bar` styles options.Rui Ueyama2018-03-016-18/+20
| | | | | | | | | GNU linkers by convention supports both `--foo bar` and `--foo=bar` styles for all long options that take arguments. Differential Revision: https://reviews.llvm.org/D43972 llvm-svn: 326506
* bpf: introduce -mattr=dwarfris to disable DwarfUsesRelocationsAcrossSectionsYonghong Song2018-03-015-2/+16
| | | | | | | | | | | | | | | | | | | | | Commit e4507fb8c94b ("bpf: disable DwarfUsesRelocationsAcrossSections") disables MCAsmInfo DwarfUsesRelocationsAcrossSections unconditionally so that dwarf will not use cross section (between dwarf and symbol table) relocations. This new debug format enables pahole to dump structures correctly as libdwarves.so does not have BPF backend support yet. This new debug format, however, breaks bcc (https://github.com/iovisor/bcc) source debug output as llvm in-memory Dwarf support has some issues to handle it. More specifically, with DwarfUsesRelocationsAcrossSections disabled, JIT compiler does not generate .debug_abbrev and Dwarf DIE (debug info entry) processing is not happy about this. This patch introduces a new flag -mattr=dwarfris (dwarf relocation in section) to disable DwarfUsesRelocationsAcrossSections. DwarfUsesRelocationsAcrossSections is true by default. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 326505
* Rename a test file and fix indentation.Rui Ueyama2018-03-012-12/+12
| | | | llvm-svn: 326504
* Set DF_TEXTREL to executables that need text relocations.Rui Ueyama2018-03-012-2/+8
| | | | | | | | | | | | | | | | | | | | | | Summary: If an executable needs text relocations, it should be marked as such so that the loader can prepare for text relocations. We currently create a dummy segment with DT_TEXTREL for that purpose. Generic ABI as of 2000 [1] mentioned that "Its [DT_TEXTREL's] use has been superseded by the DF_TEXTREL flag". However, it's actually not superseded even after 18 years. OpenBSD and musl recognize only DT_TEXTREL. So we still need to set both. [1] http://www.sco.com/developers/gabi/2000-07-17/ch5.dynamic.html Reviewers: rafael Subscribers: emaste, llvm-commits, arichardson Differential Revision: https://reviews.llvm.org/D43920 llvm-svn: 326503
* [InstCombine] allow fmul fold with less than 'fast'Sanjay Patel2018-03-012-12/+14
| | | | llvm-svn: 326502
* [NFC] Move CommentOpts checks to the call sites that depend on it.David L. Jones2018-03-016-35/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | When parsing comments, for example, for -Wdocumentation, slightly different behaviour occurs when -fparse-all-comments is specified. However, these differences are subtle: 1. All comments are saved during parsing, regardless of whether they are doc comments or not. 2. "Maybe-doc" comments, like //<, //!, etc, are saved as such, instead of marking them as ordinary comments. The maybe-doc type of comment is never saved otherwise. (Warning on these is the impetus of -Wdocumentation.) 3. All comments are treated as doc comments in ASTContext, even if they are ordinary. This change moves the logic for checking CommentOptions.ParseAllComments closer to where it has an effect. The overall logic is unchanged, but checks of the ParseAllComments flag are now done where the effect will be clearer. Reviewers: rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D43663 llvm-svn: 326501
* [DAGCombiner] When combining zero_extend of a truncate, only mask before ↵Craig Topper2018-03-0117-92/+70
| | | | | | | | | | extending for vectors. Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code. Differential Revision: https://reviews.llvm.org/D42679 llvm-svn: 326500
* [Driver] Pass -f[no-]emulated-tls and set up ExplicitEmulatedTLSChih-Hung Hsieh2018-03-016-17/+54
| | | | | | | | | | Since LLVM r326341, default EmulatedTLS mode is decided in backend according to target triple. Any front-end should pass -f[no]-emulated-tls to backend and set up ExplicitEmulatedTLS only when the flags are used. Differential Revision: https://reviews.llvm.org/D43965 llvm-svn: 326499
* Don't ingoned --enable-new-dtags.Rafael Espindola2018-03-012-2/+7
| | | | llvm-svn: 326498
* [X86][MMX] Improve handling of 64-bit MMX constantsSimon Pilgrim2018-03-014-30/+33
| | | | | | | | | | | | 64-bit MMX constant generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type. This patch bitcasts the constant to a double value to allow correct loading directly to the MMX register. I've added MMX constant asm comment support to improve testing, it's better to always print the double values as hex constants as MMX is mainly an integer unit (and even with 3DNow! its just floats). Differential Revision: https://reviews.llvm.org/D43616 llvm-svn: 326497
* [modules] Don't diagnose "redefinition" of a friend with a pending definitionRichard Smith2018-03-012-0/+48
| | | | | | if the other definition is a merged copy of the same function. llvm-svn: 326496
* [SelectionDAG] Support some SimplifySetCC cases for comparing against vector ↵Craig Topper2018-03-013-53/+36
| | | | | | | | | | | | | | splats of constants. This supports things like (setcc ugt X, 0) -> (setcc ne X, 0) I've restricted to only make changes to vectors before legalize ops because I doubt all targets have accurate condition code legality information for vectors given how little we did before. Differential Revision: https://reviews.llvm.org/D42948 llvm-svn: 326495
* [X86][AVX] Add v2f32 <-> v2i8/v2i16/v2i32 vector testsSimon Pilgrim2018-03-011-0/+342
| | | | llvm-svn: 326494
* [www] Capitalize "Clang" when referring to the project, and generalize theRichard Smith2018-03-012-22/+24
| | | | | | | | introduction on the front page page. We still use the lowercase "clang" spelling when referring to the driver binary. llvm-svn: 326493
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-016-1/+73
| | | | llvm-svn: 326492
* Add an llc testcase analogous to test/LTO/X86/strip-debug-info.llAdrian Prantl2018-03-011-0/+22
| | | | | | rdar://problem/37963669 llvm-svn: 326491
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtzMatt Arsenault2018-03-012-1/+79
| | | | | | Patch by Tom Stellard llvm-svn: 326490
* AMDGPU/GlobalISel: Define instruction mapping for G_ORMatt Arsenault2018-03-013-0/+125
| | | | | | Patch by Tom Stellard llvm-svn: 326489
* [X86][SSE] Regenerate float to/from i8/i16 vector testsSimon Pilgrim2018-03-011-20/+238
| | | | llvm-svn: 326488
* AMDGPU/GlobalISel: Remove default register mappingMatt Arsenault2018-03-011-16/+1
| | | | | | | | | This crashes for some opcodes, which prevents the SelectionDAG fallback from working. Patch by Tom Stellard llvm-svn: 326487
* [AArch64] Clean up code (NFC)Evandro Menezes2018-03-011-16/+13
| | | | | | | Clean up a couple of functions in `AArch64TargetLowering` by removing redundant statements. llvm-svn: 326486
* Added P0805 to the list of ready bitsMarshall Clow2018-03-011-2/+3
| | | | llvm-svn: 326485
* [X86][SSE] Regenerate odd sized sext/zext testsSimon Pilgrim2018-03-011-10/+158
| | | | llvm-svn: 326484
* AMDGPU/GlobalISel: Use a more correct getValueMappingMatt Arsenault2018-03-011-19/+56
| | | | | | | | | This was finding the wrong size registers for anything with more than 2 components. Patch by Tom Stellard llvm-svn: 326483
* AMDGPU/GlobalISel: Define instruction mapping for G_BITCASTMatt Arsenault2018-03-012-0/+37
| | | | | | Patch by Tom Stellard llvm-svn: 326482
* AMDGPU/GlobalISel: Mark i32->i64 zext as legalMatt Arsenault2018-03-012-0/+17
| | | | llvm-svn: 326481
* [AArch64] Add support for secrel add/load/store relocations for COFFMartin Storsjo2018-03-017-4/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D43288 llvm-svn: 326480
* AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.comprMatt Arsenault2018-03-012-4/+83
| | | | | | Patch by Tom Stellard llvm-svn: 326479
* [MinGW] Fix --{start,end}-group.Rui Ueyama2018-03-012-2/+4
| | | | | | | | Currently --start-group=foo is accidentally accepted by the MinGW driver. Differential Revision: https://reviews.llvm.org/D43836 llvm-svn: 326478
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.expMatt Arsenault2018-03-012-1/+98
| | | | | | Patch by Tom Stellard llvm-svn: 326477
* [RecordLayout] Only assert that fundamental type sizes are power of two on MSVCMartin Storsjo2018-03-013-4/+47
| | | | | | | | | | Make types with sizes that aren't a power of two an error (that can be disabled) in structs with ms_struct layout, except on mingw where the situation is quite likely to occur and GCC handles it silently. Differential Revision: https://reviews.llvm.org/D43908 llvm-svn: 326476
* [SimplifyLibCalls] Update an obviously copy and pasted header comment to ↵Craig Topper2018-03-011-4/+2
| | | | | | match this file. NFC llvm-svn: 326475
* [InstCombine] Auto-generate complete checks. NFCCraig Topper2018-03-011-141/+246
| | | | llvm-svn: 326474
* AMDGPU/GlobalISel: Define InstrMappings for G_ICMPMatt Arsenault2018-03-015-15/+168
| | | | | | Patch by Tom Stellard llvm-svn: 326472
* AMDGPU/GlobalISel: Make i32 mul legalMatt Arsenault2018-03-012-0/+19
| | | | llvm-svn: 326471
* AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEFMatt Arsenault2018-03-013-6/+35
| | | | | | Patch by Tom Stellard llvm-svn: 326470
* Driver: hoist `-fno-rtti-data` to a driver flagSaleem Abdulrasool2018-03-013-2/+4
| | | | | | | | This is needed for building with the GNU driver (`clang++`) when targeting Windows and using msvcprt. This flag is the equivalent of `/GR-`. llvm-svn: 326469
* AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANTMatt Arsenault2018-03-012-0/+32
| | | | | | Patch by Tom Stellard llvm-svn: 326468
* AMDGPU/GlobalISel: Add copyCost for VGPR->SGPR copiesMatt Arsenault2018-03-011-4/+7
| | | | | | Patch by Tom Stellard llvm-svn: 326467
* AMDGPU/GlobalISel: Make i32 xor legalMatt Arsenault2018-03-012-2/+20
| | | | llvm-svn: 326466
* AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legalMatt Arsenault2018-03-012-0/+39
| | | | | | Patch by Tom Stellard llvm-svn: 326465
* AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legalMatt Arsenault2018-03-012-0/+17
| | | | | | Patch by Tom Stellard llvm-svn: 326464
* Correct man page description for --section-startEd Maste2018-03-011-1/+1
| | | | | | | | | The argument is section=address, not just address. (For compatibility with GNU linkers we need to, but do not yet, accept --section-start=section=address.) llvm-svn: 326463
* [analyzer] Enable cfg-temporary-dtors by default.Artem Dergachev2018-03-017-11/+12
| | | | | | | | | | | | Don't enable c++-temp-dtor-inlining by default yet, due to this reference counting pointe problem. Otherwise the new mode seems stable and allows us to incrementally fix C++ problems in much less hacky ways. Differential Revision: https://reviews.llvm.org/D43804 llvm-svn: 326461
* [WebAssembly] Fix broken gcc build after rL326454Sam Clegg2018-03-013-13/+14
| | | | | | | The gcc builders were broken by rL326454 See: https://reviews.llvm.org/D43921 llvm-svn: 326460
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