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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-01 19:09:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-01 19:09:21 +0000 |
| commit | 3f6a204eaa4a1534cd5052b82f976f4628a6deb1 (patch) | |
| tree | 38c1f8b1de8d557aadf73bd5422b7635e20e36c4 | |
| parent | 8e80a5fbcabc6eaa297b839b66fb44d6c07474db (diff) | |
| download | bcm5719-llvm-3f6a204eaa4a1534cd5052b82f976f4628a6deb1.tar.gz bcm5719-llvm-3f6a204eaa4a1534cd5052b82f976f4628a6deb1.zip | |
AMDGPU/GlobalISel: Make i32 xor legal
llvm-svn: 326466
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 18 |
2 files changed, 20 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 269aac69521..35aa373138f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -35,6 +35,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() { setAction({G_ADD, S32}, Legal); setAction({G_AND, S32}, Legal); + setAction({G_OR, S32}, Legal); + setAction({G_XOR, S32}, Legal); setAction({G_BITCAST, V2S16}, Legal); setAction({G_BITCAST, 1, S32}, Legal); @@ -79,8 +81,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() { setAction({G_LOAD, 1, P1}, Legal); setAction({G_LOAD, 1, P2}, Legal); - setAction({G_OR, S32}, Legal); - setAction({G_SELECT, S32}, Legal); setAction({G_SELECT, 1, S1}, Legal); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir new file mode 100644 index 00000000000..b7838f84580 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir @@ -0,0 +1,18 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- +name: test_xor +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: test_xor + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]] + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = G_XOR %0, %1 + $vgpr0 = COPY %2 +... |
