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* Not all blocks are reachable from entry. Don't assume they are.Nick Lewycky2019-04-012-4/+51
| | | | | | Fixes a bug in isPotentiallyReachable, noticed by inspection. llvm-svn: 357425
* [API] Add SBReproducer to LLDB.hJonas Devlieghere2019-04-011-0/+1
| | | | llvm-svn: 357424
* [libcxx] Make sure reference_wrapper works with incomplete typesLouis Dionne2019-04-015-1/+163
| | | | | | | | | | | | Summary: Completes P0357R3, which was merged into the C++20 Working Draft in San Diego. Reviewers: EricWF, mclow.lists Subscribers: christof, jkorous, dexonsmith, libcxx-commits Differential Revision: https://reviews.llvm.org/D54722 llvm-svn: 357423
* [pstl] Mangle the parallel_strict_scan backend functionLouis Dionne2019-04-013-8/+9
| | | | llvm-svn: 357422
* [NFC][LLD] Specify namespaces explicity to fix build failure on GCC 5 after ↵Matthew Voss2019-04-011-3/+7
| | | | | | r357383 llvm-svn: 357421
* [Process] Fix WriteMemory return valueMed Ismail Bennani2019-04-012-2/+32
| | | | | | | | | | | | | | | | | | | | | Summary: In case of a breakpoint site overlapping with the destination address, the WriteMemory method reported an incorrect memory size. Instead of returning the right amount of bytes written, it falls through the scope and returned 0. Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com> Reviewers: jasonmolenda, friss, jingham Subscribers: JDevlieghere, davide, lldb-commits, #lldb Tags: #lldb Differential Revision: https://reviews.llvm.org/D60022 llvm-svn: 357420
* [X86] Classify the AVX512 rounding control operand as ↵Craig Topper2019-04-013-2/+9
| | | | | | | | | | X86::OPERAND_ROUNDING_CONTROL instead of MCOI::OPERAND_IMMEDIATE. Add an assert on legal values of rounding control in the encoder and remove an explicit mask. This should allow llvm-exegesis to intelligently constrain the rounding mode. The mask in the encoder shouldn't be necessary any more. We used to allow codegen to use 8-11 for rounding mode and the assembler would use 0-3 to mean the same thing so we masked here and in the printer. Codegen now matches the assembler and the printer was updated, but I forgot to update the encoder. llvm-svn: 357419
* [llvm-objcopy] Add --keep-symbols optionYi Kong2019-04-013-0/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D60054 llvm-svn: 357418
* ELF: Perform per-section .ARM.exidx processing during ↵Peter Collingbourne2019-04-013-54/+56
| | | | | | | | | | | | combineEhFrameSections(). NFCI. And rename the function to combineEhSections(). This makes the processing of .ARM.exidx even more similar to .eh_frame and means that we can avoid an additional loop over InputSections. Differential Revision: https://reviews.llvm.org/D60026 llvm-svn: 357417
* [SLP] getVectorElementSize and isTreeTinyAndNotFullyVectorizable are const ↵Simon Pilgrim2019-04-011-4/+4
| | | | | | methods. NFCI. llvm-svn: 357416
* [CodeGen] Generate follow-up metadata for loops with more than one ↵Michael Kruse2019-04-0111-126/+668
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | transformation. Before this patch, CGLoop would dump all transformations for a loop into a single LoopID without encoding any order in which to apply them. rL348944 added the possibility to encode a transformation order using followup-attributes. When a loop has more than one transformation, use the follow-up attribute define the order in which they are applied. The emitted order is the defacto order as defined by the current LLVM pass pipeline, which is: LoopFullUnrollPass LoopDistributePass LoopVectorizePass LoopUnrollAndJamPass LoopUnrollPass MachinePipeliner This patch should therefore not change the assembly output, assuming that all explicit transformations can be applied, and no implicit transformations in-between. In the former case, WarnMissedTransformationsPass should emit a warning (except for MachinePipeliner which is not implemented yet). The latter could be avoided by adding 'llvm.loop.disable_nonforced' attributes. Because LoopUnrollAndJamPass processes a loop nest, generation of the MDNode is delayed to after the inner loop metadata have been processed. A temporary LoopID is therefore used to annotate instructions and RAUW'ed by the actual LoopID later. Differential Revision: https://reviews.llvm.org/D57978 llvm-svn: 357415
* [SLP] getGatherCost and isFullyVectorizableTinyTree are const methods. NFCI.Simon Pilgrim2019-04-011-7/+7
| | | | llvm-svn: 357414
* Fix PR#41323 'Race condition in steady_clock::now for _LIBCPP_WIN32API'. ↵Marshall Clow2019-04-011-6/+15
| | | | | | thanks to Ivan Afanasyev for the report. llvm-svn: 357413
* [OPENMP]Allocate clause allocator in target region.Alexey Bataev2019-04-013-0/+18
| | | | | | | | | | According to OpenMP 5.0, 2.11.4 allocate Clause, Restrictions, allocate clauses that appear on a target construct or on constructs in a target region must specify an allocator expression unless a requires directive with the dynamic_allocators clause is present in the same compilation unit. Patch adds a check for this restriction. llvm-svn: 357412
* [libc++] Declare std::tuple_element as struct instead of classLouis Dionne2019-04-019-32/+19
| | | | | | | | | | | | Similarly to https://reviews.llvm.org/rL350972, this revision changes std::tuple_element from class to struct. Fixes PR41331. Thanks to Jan Wilken Dörrie for the patch. Differential Revision: https://reviews.llvm.org/D60069 llvm-svn: 357411
* Fix PR41130 - 'operator/ of std::chrono::duration and custom type'. Thanks ↵Marshall Clow2019-04-019-28/+139
| | | | | | to Zulan for the report, and Howard for the direction of the fix. llvm-svn: 357410
* Commit accidentally omitted test case.Caroline Tice2019-04-011-0/+59
| | | | | | | | This test case was approved as part of https://reviews.llvm.org/D49434, but was accidentally omitted from the final commit. llvm-svn: 357409
* [LoopPred] Be uniform about proving generated conditionsPhilip Reames2019-04-012-0/+52
| | | | | | We'd been optimizing the case where the predicate was obviously true, do the same for the false case. Mostly just for completeness sake, but also may improve compile time in loops which will exit through the guard. Such loops are presumed rare in fastpath code, but may be present down untaken paths, so optimizing for them is still useful. llvm-svn: 357408
* [NVPTX] Fix the codegen for llvm.round.Bixia Zheng2019-04-016-22/+128
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, we translate llvm.round to PTX cvt.rni, which rounds to the even interger when the source is equidistant between two integers. This is not correct as llvm.round should round away from zero. This change replaces llvm.round with a round away from zero implementation through target specific custom lowering. Modify a few affected tests to not check for cvt.rni. Instead, we check for the use of a few constants used in implementing round. We are also adding CUDA runnable tests to check for the values produced by llvm.round to test-suites/External/CUDA. Reviewers: tra Subscribers: jholewinski, sanjoy, jlebar, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59947 llvm-svn: 357407
* [LoopPred] Delete the old condition expressions if unusedPhilip Reames2019-04-019-202/+7
| | | | | | LoopPredication was replacing the original condition, but leaving the instructions to compute the old conditions around. This would get cleaned up by other passes of course, but we might as well do it eagerly. That also makes the test output less confusing. llvm-svn: 357406
* Attempt to fix failing buildbot (ppc64le)Gabor Marton2019-04-011-0/+1
| | | | llvm-svn: 357405
* [Tests] Autogen all the LoopPredication testsPhilip Reames2019-04-017-388/+1912
| | | | | | I'm about to make some changes to the pass which cause widespread - but uninteresting - test diffs. Prepare the tests for easy updating. llvm-svn: 357404
* [Tests] Add tests for a possible loop predication transform variantPhilip Reames2019-04-011-0/+247
| | | | | | As highlighted by tests, if one of the operands is loop variant, but guaranteed to have the same value on all iterations, we have a missed oppurtunity. llvm-svn: 357403
* [ASTImporter] Convert ODR diagnostics inside ASTImporter implementationGabor Marton2019-04-011-14/+14
| | | | | | | | | | | | | | | | | | | | | | Summary: ASTStructuralEquivalence uses a flag to indicate whether ODR diagnostics should be considered errors or warnings as module Sema is more strict than ASTMerge. The implementation of ASTImporter should allso follow along the same lines. Reviewers: martong, a.sidorin, shafik, a_sidorin Reviewed By: shafik, a_sidorin Subscribers: rnkovacs, martong, dkrupp, Szelethus, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D59761 Patch by Endre Fulop! llvm-svn: 357402
* [pstl] Indent preprocessor directives as part of the clang-format rulesLouis Dionne2019-04-0111-73/+76
| | | | | | | | | | | | | | | Summary: Indenting preprocessor directives provides a significant gain in readability. We do it for normal if statements, and it makes sense to do it for preprocessor ifs too. Reviewers: rodgert, MikeDvorskiy Subscribers: jkorous, dexonsmith, jdoerfert, libcxx-commits Differential Revision: https://reviews.llvm.org/D59767 llvm-svn: 357401
* [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning2019-04-0119-640/+475
| | | | | | | | | | | | | | | | | | | | | | | This change incorporates an effort by Connor Abbot to change how we deal with WWM operations potentially trashing valid values in inactive lanes. Previously, the SIFixWWMLiveness pass would work out which registers were being trashed within WWM regions, and ensure that the register allocator did not have any values it was depending on resident in those registers if the WWM section would trash them. This worked perfectly well, but would cause sometimes severe register pressure when the WWM section resided before divergent control flow (or at least that is where I mostly observed it). This fix instead runs through the WWM sections and pre allocates some registers for WWM. It then reserves these registers so that the register allocator cannot use them. This results in a significant register saving on some WWM shaders I'm working with (130 -> 104 VGPRs, with just this change!). Differential Revision: https://reviews.llvm.org/D59295 llvm-svn: 357400
* [lldb] [Process/elf-core] Support aarch64 NetBSD core dumpsMichal Gorny2019-04-0110-0/+49
| | | | | | | | | | | Include support for NetBSD core dumps from evbarm/aarch64 system, and matching test cases for them. Based on earlier work by Kamil Rytarowski. Differential Revision: https://reviews.llvm.org/D60034 llvm-svn: 357399
* gn build: Merge r357383Nico Weber2019-04-011-0/+1
| | | | llvm-svn: 357398
* [AArch64] Add v8.5-a Memory Tagging STZGM instructionDavid Spickett2019-04-014-0/+53
| | | | | | | | | | | | | | | This instruction writes a block of allocation tags and stores zero to the associated data locations. It differs from STGM by 1 bit and has the same arguments. The specification can be found here: https://developer.arm.com/docs/ddi0596/c Differential Revision: https://reviews.llvm.org/D60065 llvm-svn: 357397
* [RISCV] Attach VK_RISCV_CALL to symbols upon creationAlex Bradbury2019-04-016-9/+57
| | | | | | | | | | | | | | | | | This patch replaces the addition of VK_RISCV_CALL in RISCVMCCodeEmitter by creating the RISCVMCExpr when tail/call are parsed, or in the codegen case when the callee symbols are created. This required adding a new CallSymbol operand to allow only adding VK_RISCV_CALL to tail/call instructions. This patch will allow further expansion of parsing and codegen to easily include PLT symbols which must generate the R_RISCV_CALL_PLT relocation. Differential Revision: https://reviews.llvm.org/D55560 Patch by Lewis Revill. llvm-svn: 357396
* [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructionsDavid Spickett2019-04-018-105/+52
| | | | | | | | | | | | | | The STGV/LDGV instructions were replaced with STGM/LDGM. The encodings remain the same but there is no longer writeback so there are no unpredictable encodings to check for. The specfication can be found here: https://developer.arm.com/docs/ddi0596/c Differential Revision: https://reviews.llvm.org/D60064 llvm-svn: 357395
* [ASTImporter] Make ODR error handling configurableGabor Marton2019-04-014-59/+178
| | | | | | | | | | | | | | | | | | | | | Summary: ODR errors are not necessarily true errors during the import of ASTs. ASTMerge and CrossTU should use the warning equivalent of every CTU error, while Sema should emit errors as before. Reviewers: martong, a_sidorin, shafik, a.sidorin Reviewed By: a_sidorin Subscribers: rnkovacs, dkrupp, Szelethus, jdoerfert, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D58897 Patch by Endre Fulop! llvm-svn: 357394
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-019-36/+205
| | | | | | | | | | | | | | | | | This patch adds an implementation of a PC-relative addressing sequence to be used when -mcmodel=medium is specified. With absolute addressing, a 'medium' codemodel may cause addresses to be out of range. This is because while 'medium' implies a 2 GiB addressing range, this 2 GiB can be at any offset as opposed to 'small', which implies the first 2 GiB only. Note that LLVM/Clang currently specifies code models differently to GCC, where small and medium imply the same functionality as GCC's medlow and medany respectively. Differential Revision: https://reviews.llvm.org/D54143 Patch by Lewis Revill. llvm-svn: 357393
* [AArch64] Add v8.5-a Memory Tagging GMID_EL1 registerDavid Spickett2019-04-014-0/+32
| | | | | | | | | | | The latest version of the MTE spec added a system register 'GMID_EL1'. It contains the block size used by the LDGM and STGM instructions and is read only. The specification can be found here: https://developer.arm.com/docs/ddi0596/c llvm-svn: 357392
* Fix builder.Alexandre Ganea2019-04-011-2/+2
| | | | | | http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/24702/steps/check-fuzzer/logs/stdio llvm-svn: 357391
* [OPENMP] Check that allocated variables are used in private clauses.Alexey Bataev2019-04-013-131/+230
| | | | | | | | | | According to OpenMP 5.0 standard, 2.11.4 allocate Clause, Restrictions, For any list item that is specified in the allocate clause on a directive, a data-sharing attribute clause that may create a private copy of that list item must be specified on the same directive. Patch adds the checks for this restriction. llvm-svn: 357390
* [InstCombine] Handle vector gep with scalar argument in ↵Mikael Holmen2019-04-012-1/+24
| | | | | | | | | | | | | | | | | | | | | | | evaluateInDifferentElementOrder Summary: This fixes PR41270. The recursive function evaluateInDifferentElementOrder expects to be called on a vector Value, so when we call it on a vector GEP's arguments, we must first check that the argument is indeed a vector. Reviewers: reames, spatel Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60058 llvm-svn: 357389
* X86: Fix override warningMatt Arsenault2019-04-011-2/+2
| | | | llvm-svn: 357388
* Revert "[InstCombine] Handle vector gep with scalar argument in ↵Mikael Holmen2019-04-012-24/+1
| | | | | | | | | | | evaluateInDifferentElementOrder" This reverts commit 75216a6dbcfe5fb55039ef06a07e419fa875f4a5. I'll recommit with a better commit message with reference to the phabricator review. llvm-svn: 357387
* InstSimplify: Add baseline test for upcoming changeMatt Arsenault2019-04-011-0/+120
| | | | llvm-svn: 357386
* [InstCombine] Handle vector gep with scalar argument in ↵Mikael Holmen2019-04-012-1/+24
| | | | | | | | | | | | evaluateInDifferentElementOrder This fixes PR41270. The recursive function evaluateInDifferentElementOrder expects to be called on a vector Value, so when we call it on a vector GEP's arguments, we must first check that the argument is indeed a vector. llvm-svn: 357385
* [X86] Make post-ra scheduling macrofusion-aware.Clement Courbet2019-04-013-2/+11
| | | | | | | | | | Subscribers: MatzeB, arsenm, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59688 llvm-svn: 357384
* [LLD][COFF] Early dependency detectionAlexandre Ganea2019-04-016-59/+238
| | | | | | | | | | | | We introduce a new class hierarchy for debug types merging (in DebugTypes.h). The end-goal is to parallelize the type merging - please see the plan in D59226. Previously, dependency discovery was done on the fly, much later, during the type merging loop. Unfortunately, parallelizing the type merging requires the dependencies to be merged in first, before any dependent ObjFile, thus this early discovery. The overall intention for this path is to discover debug information dependencies at a much earlier stage, when processing input files. Currently, two types of dependency are supported: PDB type servers (when compiling with MSVC /Zi) and precompiled headers OBJs (when compiling with MSVC /Yc and /Yu). Once discovered, an explicit link is added into the dependent ObjFile, through the new debug types class hierarchy introduced in DebugTypes.h. Differential Revision: https://reviews.llvm.org/D59053 llvm-svn: 357383
* [InstCombine] eliminate commuted select-shuffles + binop (PR41304)Sanjay Patel2019-04-012-20/+75
| | | | | | | | | | | | | | | | | | | | | | | If we have a commutable vector binop with inverted select-shuffles, we don't care about the order of the operands in each vector lane: LHS = shuffle V1, V2, <0, 5, 6, 3> RHS = shuffle V2, V1, <0, 5, 6, 3> LHS + RHS --> <V1[0]+V2[0], V2[1]+V1[1], V2[2]+V1[2], V1[3]+V2[3]> --> V1 + V2 PR41304: https://bugs.llvm.org/show_bug.cgi?id=41304 ...is currently titled as an SLP enhancement, but at least for the given example, we can reduce that in instcombine because we are just eliminating shuffles. As noted in the TODO, this could be generalized, but I haven't thought through those patterns completely, so this is limited to what appears to be always safe. Differential Revision: https://reviews.llvm.org/D60048 llvm-svn: 357382
* [X86MacroFusion][NFC] Add more tests.Clement Courbet2019-04-011-105/+198
| | | | | | In preparation for D59688. llvm-svn: 357381
* [X86] Fix a test from r357317Krasimir Georgiev2019-04-011-1/+1
| | | | | | | | | | | | | | | | | | Summary: The missing `<` causes the lld command to override the test file, which fails in environments marking the test files as readonly. Reviewers: bkramer Reviewed By: bkramer Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60060 llvm-svn: 357380
* [X86][SSE] Add fcmp constant folding testsSimon Pilgrim2019-04-011-0/+278
| | | | | | Initial test coverage for D60006 llvm-svn: 357379
* [RISCV] Add seto pattern expansionLuis Marques2019-04-019-51/+11
| | | | | | | | | Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and `fcmp ord` would be inefficient due to an unoptimized double negation. Differential Revision: https://reviews.llvm.org/D59699 llvm-svn: 357378
* [ELF] Rename SyntheticSection::empty to more appropriate isNeeded() with ↵Fangrui Song2019-04-013-41/+41
| | | | | | | | | | | | | | | | | | | | | | | opposite meaning Summary: Some synthetic sections can be empty while still being needed, thus they can't be removed by removeUnusedSyntheticSections(). Rename this member function to more appropriate isNeeded() with the opposite meaning. No functional change intended. Reviewers: ruiu, espindola Reviewed By: ruiu Subscribers: jhenderson, grimar, emaste, arichardson, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59982 llvm-svn: 357377
* [Linux/x86] Fix writing of non-gpr registers on newer processorsPavel Labath2019-04-012-51/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We're using ptrace(PTRACE_SETREGSET, NT_X86_XSTATE) to write all non-gpt registers on x86 linux. Unfortunately, this method has a quirk, where the kernel rejects all attempts to write to this area if one supplies a buffer which is smaller than the area size (even though the kernel will happily accept partial reads from it). This means that if the CPU supports some new registers/extensions that we don't know about (in my case it was the PKRU extension), we will fail to write *any* non-gpr registers, even those that we know about. Since this is a situation that's likely to appear again and again, I add code to NativeRegisterContextLinux_x86_64 to detect the runtime size of the area, and allocate an appropriate buffer. This does not mean that we will start automatically supporting all new extensions, but it does mean that the new extensions will not prevent the old ones from working. This fixes tests attempting to write to non-gpr registers on new intel processors (cca Kaby Lake Refresh). Reviewers: jankratochvil, davezarzycki Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D59991 llvm-svn: 357376
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