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* [mips] Fix the definition of sync, synciSimon Dardis2018-04-2515-18/+78
| | | | | | | | | | Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
* [llvm-mca] Default to the native host cpu if flag -mcpu is not specified.Andrea Di Biagio2018-04-253-6/+9
| | | | llvm-svn: 330809
* add check for long double for __builtin_dump_structPaul Semel2018-04-251-0/+24
| | | | llvm-svn: 330808
* [llvm-mca] Remove method Instruction::isZeroLatency(). NFCIAndrea Di Biagio2018-04-255-13/+11
| | | | llvm-svn: 330807
* [LoopInterchange] Use getExitBlock()/getExitingBlock instead of manual impl.Florian Hahn2018-04-252-37/+74
| | | | | | | | | | | | | | | This also means we have to check if the latch is the exiting block now, as `transform` expects the latches to be the exiting blocks too. https://bugs.llvm.org/show_bug.cgi?id=36586 Reviewers: efriedma, davide, karthikthecool Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D45279 llvm-svn: 330806
* [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing ↵Sander de Smalen2018-04-254-8/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | modes. This patch adds parsing support for 'vector + shift/extend' and corresponding asm operand classes, needed for implementing SVE's gather/scatter addressing modes. The added combinations of vector (ZPR) and Shift/Extend are: Unscaled: ZPR64ExtLSL8: signed 64-bit offsets (z0.d) ZPR32ExtUXTW8: unsigned 32-bit offsets (z0.s, uxtw) ZPR32ExtSXTW8: signed 32-bit offsets (z0.s, sxtw) Unpacked and unscaled: ZPR64ExtUXTW8: unsigned 32-bit offsets (z0.d, uxtw) ZPR64ExtSXTW8: signed 32-bit offsets (z0.d, sxtw) Unpacked and scaled: ZPR64ExtUXTW<scale>: unsigned 32-bit offsets (z0.d, uxtw #<shift>) ZPR64ExtSXTW<scale>: signed 32-bit offsets (z0.d, sxtw #<shift>) Scaled: ZPR32ExtUXTW<scale>: unsigned 32-bit offsets (z0.s, uxtw #<shift>) ZPR32ExtSXTW<scale>: signed 32-bit offsets (z0.s, sxtw #<shift>) ZPR64ExtLSL<scale>: unsigned 64-bit offsets (z0.d, lsl #<shift>) ZPR64ExtLSL<scale>: signed 64-bit offsets (z0.d, lsl #<shift>) Patch [1/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45951 llvm-svn: 330805
* [DebugInfo] Invalidate debug info in ReassociatePass::RewriteExprTreeBjorn Pettersson2018-04-252-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When Reassociate is rewriting an expression tree it may reuse old binary expression nodes, for new expressions. Whenever an expression node is reused, but with a non-trivial change in the result, we need to invalidate any debug info that is associated with the node. If for example rewriting x = mul a, b y = mul c, x into x = mul c, b y = mul a, x we still get the same result for 'y', but 'x' is a new expression. All debug info referring to 'x' must be invalidated (marked as optimized out) since we no longer calculate the expected value. As a side-effect this patch avoid (at least some) problems where reassociate could end up creating IR with debug-use before def. Earlier the dbg.value nodes where left untouched in the IR, while the reused binary nodes where sinked to just before the root node of the rewritten expression tree. See PR27273 for more info about such problems. Reviewers: dblaikie, aprantl, dexonsmith Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D45975 llvm-svn: 330804
* [clangd] Minor fixes for C++ standard library header mapping.Eric Liu2018-04-251-7/+24
| | | | llvm-svn: 330803
* Fix buildbot problems after rC330794Bjorn Pettersson2018-04-251-1/+2
| | | | | | | | | | | | | | Avoiding error: no matching function for call to 'makeArrayRef' at ../tools/clang/lib/Parse/ParseTemplate.cpp:373:17 By using a local C array as input to makeArrayRef. Not sure if this is the best solution, but it makes the code compile again. llvm-svn: 330802
* [TableGen] Fix bad indentation in tablegen output file.Craig Topper2018-04-251-2/+2
| | | | llvm-svn: 330801
* Update isl to isl-0.19-114-g385262afTobias Grosser2018-04-2513-41/+248
| | | | llvm-svn: 330800
* Merging r46043:David Bolvansky2018-04-251-3/+3
| | | | | | ------------------------------------------------------------------------ llvm-svn: 330799
* [NFC] Make dependent parameter non-deducible, so that we are forced to use ↵Faisal Vali2018-04-251-1/+2
| | | | | | | | the default template parameter. This might provide users with more graceful diagnostics if they should ever try and call this function with non-ConceptDecls. llvm-svn: 330798
* [X86] Auto-generate complete checks. NFCCraig Topper2018-04-251-53/+178
| | | | llvm-svn: 330797
* Fix rC330794 - a parameter that should have been dependent was inadvertently ↵Faisal Vali2018-04-251-2/+4
| | | | | | | | | | not - and compiled in MSVC - but not so for the other bots. The fix was to make it dependent as intended. llvm-svn: 330796
* Fix lit test kernel-call.cu failure on ps4 due to dso_localYaxun Liu2018-04-251-2/+2
| | | | llvm-svn: 330795
* [c++2a] [concepts] Add rudimentary parsing support for template concept ↵Faisal Vali2018-04-2533-72/+635
| | | | | | | | | | | | | | declarations This patch is a tweak of changyu's patch: https://reviews.llvm.org/D40381. It differs in that the recognition of the 'concept' token is moved into the machinery that recognizes declaration-specifiers - this allows us to leverage the attribute handling machinery more seamlessly. See the test file to get a sense of the basic parsing that this patch supports. There is much more work to be done before concepts are usable... Thanks Changyu! llvm-svn: 330794
* Fix failure in lit test kernel-call.cuYaxun Liu2018-04-251-1/+1
| | | | | | There is signext on ppc64. Just remove check for function argument. llvm-svn: 330793
* [DivRemPairs] Fix non-determinism in use list order.Geoff Berry2018-04-251-3/+8
| | | | | | | | | | | | | | | | | Summary: Use a MapVector instead of a DenseMap for RemMap since it is iteratated over and the order of iteration can effect the order that new instructions are created. This can in turn effect the use list order of div/rem input values if multiple new instructions are created that share any input values. Reviewers: spatel Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D45858 llvm-svn: 330792
* [libcxx] [test] Remove nonportable that errc::is_a_directory produces "Is a ↵Billy Robert O'Neal III2018-04-252-2/+6
| | | | | | | | | | directory" from ios_base::failure tests These io_error asserts that std::errc::is_a_directory has message "Is a directory". On MSVC++ it reports "is a directory" (with a lowercase I). That doesn't matter for the ios_failure component being tested, so just implement in terms of system_category().message(). Reviewed as https://reviews.llvm.org/D45715 llvm-svn: 330791
* [HIP] Add hip input kind and codegen for kernel launchingYaxun Liu2018-04-2513-67/+151
| | | | | | | | | | | | | | | | | | | | | | | HIP is a language similar to CUDA (https://github.com/ROCm-Developer-Tools/HIP/blob/master/docs/markdown/hip_kernel_language.md ). The language syntax is very similar, which allows a hip program to be compiled as a CUDA program by Clang. The main difference is the host API. HIP has a set of vendor neutral host API which can be implemented on different platforms. Currently there is open source implementation of HIP runtime on amdgpu target (https://github.com/ROCm-Developer-Tools/HIP). This patch adds support of input kind and language standard hip. When hip file is compiled, both LangOpts.CUDA and LangOpts.HIP is turned on. This allows compilation of hip program as CUDA in most cases and only special handling of hip program is needed LangOpts.HIP is checked. This patch also adds support of kernel launching of HIP program using HIP host API. When -x hip is not specified, there is no behaviour change for CUDA. Patch by Greg Rodgers. Revised and lit test added by Yaxun Liu. Differential Revision: https://reviews.llvm.org/D44984 llvm-svn: 330790
* [ODRHash] Hash template arguments of methods.Richard Trieu2018-04-254-1/+219
| | | | llvm-svn: 330789
* Bring r329960 back.Rafael Espindola2018-04-253-62/+50
| | | | | | | | | | | | | | | | | | | | The fix is to copy Used when replacing the symbol. Original message: Do not keep shared symbols created from garbage-collected eliminated DSOs. If all references to a DSO happen to be weak, and if the DSO is specified with --as-needed, the DSO is not added to DT_NEEDED. If that happens, we also need to eliminate shared symbols created from the DSO. Otherwise, they become dangling references that point to non-exsitent DSO. Fixes https://bugs.llvm.org/show_bug.cgi?id=36991 Differential Revision: https://reviews.llvm.org/D45536 llvm-svn: 330788
* [PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use the newChandler Carruth2018-04-251-70/+78
| | | | | | | | | | | | | | | | | | | | | | | update API for dominators rather than doing manual, hacky updates. This is just the first step, but in some ways the most important as it moves the non-trivial unswitching to update the domtree rather than fully recalculating it each time. Subsequent patches should remove the custom update logic used by the trivial unswitch and replace it with uses of the update API. This also fixes a number of bugs I was seeing when testing non-trivial unswitch due to it querying the quasi-correct dominator tree. Now the tree is 100% correct and safe to query. That said, there are still more bugs I can see with non-trivial unswitch just running over the test suite, so more bugfix patches are needed as well. Thanks to both Sanjoy and Fedor for reviews and testing! Differential Revision: https://reviews.llvm.org/D45943 llvm-svn: 330787
* [COFF] create MemoryBuffers without requiring NUL terminatorsBob Haarman2018-04-241-3/+7
| | | | | | | | | | | | | | | | | | | | Summary: In a number of places in the COFF linker, we were calling MemoryBuffer::getFile() with default parameters. This causes LLVM to NUL-terminate the buffers, which can prevent them from being memory mapped. Since we operate on binary and do not use NUL as an indicator of the end of the file content, this change causes us to not require the NUL terminator anymore. Reviewers: ruiu, pcc Reviewed By: ruiu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45909 llvm-svn: 330786
* Style fix.Rui Ueyama2018-04-241-3/+3
| | | | llvm-svn: 330785
* Add a test. NFC.Rafael Espindola2018-04-241-0/+21
| | | | | | This would have found the issue in r329960. llvm-svn: 330784
* [MachineOutliner] Check for explicit uses of LR/W30 in MI operandsJessica Paquette2018-04-242-0/+62
| | | | | | | | | | Before, the outliner would grab ADRPs that used LR/W30. This patch fixes that by checking for explicit uses of those registers before the special-casing for ADRPs. This also adds a test that ensures that those sorts of ADRPs won't be outlined. llvm-svn: 330783
* [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legalCraig Topper2018-04-2413-90/+91
| | | | | | | | | | | | We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets. Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue. This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here. Differential Revision: https://reviews.llvm.org/D45585#inline-402825 llvm-svn: 330781
* Revert "[Driver] Android triples are not aliases for other triples."Dan Albert2018-04-242-111/+50
| | | | | | | | Revering while I diagnose the failures. This reverts commit 82dc3bf2157da280420f80e654292cb05e0dc5f7. llvm-svn: 330780
* Fix path separator checks on WindowsReid Kleckner2018-04-241-1/+1
| | | | llvm-svn: 330779
* [X86] Account for partial stack slot spills (PR30821)Warren Ristow2018-04-245-81/+289
| | | | | | | | | | | | | | | | | | | | | | | Previously, _any_ store or load instruction was considered to be operating on a spill if it had a frameindex as an operand, and thus was fair game for optimisations such as "StackSlotColoring". This usually works, except on architectures where spills can be partially restored, for example on X86 where a spilt vector can have a single component loaded (zeroing the rest of the target register). This can be mis-interpreted and the zero extension unsoundly eliminated, see pr30821. To avoid this, this commit optionally provides the caller to isLoadFromStackSlot and isStoreToStackSlot with the number of bytes spilt/loaded by the given instruction. Optimisations can then determine that a full spill followed by a partial load (or vice versa), for example, cannot necessarily be commuted. Patch by Jeremy Morse! Differential Revision: https://reviews.llvm.org/D44782 llvm-svn: 330778
* [llvm-objcopy] Adjust the help messageAlexander Shaposhnikov2018-04-241-3/+3
| | | | | | | | | | Capitalize the first letter, make the text a bit more consistent. NFC. Differential revision: https://reviews.llvm.org/D46025 llvm-svn: 330777
* Bring back APInt self-move assignment check for MSVC onlyReid Kleckner2018-04-242-0/+37
| | | | | | | | | | | | | | | | | Summary: It was removed about a year ago in r300477. Bring it back, along with its unittest, when the MSVC STL is in use. The MSVC STL performs self-assignment in std::shuffle. These days, llvm::sort calls std::shuffle when expensive checks are enabled to help find non-determinism bugs. Reviewers: craig.topper, chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46028 llvm-svn: 330776
* AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsicTom Stellard2018-04-245-34/+6
| | | | | | | | | | | | | | Summary: This is no longer used by mesa since its 18.0.0 release. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D45988 llvm-svn: 330775
* AMDGPU/GlobalISel: Fall-back to SelectionDAG for non-void functionsTom Stellard2018-04-242-0/+14
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45843 llvm-svn: 330774
* [docs] Add a note on non-deterministic sorting order of equal elementsMandeep Singh Grang2018-04-241-0/+11
| | | | | | | | | | | | Reviewers: RKSimon, t.p.northover, dexonsmith Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45831 llvm-svn: 330773
* [clang-tidy] Improve bugprone-unused-return-value checkJonathan Coe2018-04-244-14/+106
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add support for checking class template member functions. Also add the following functions to be checked by default: - std::unique_ptr::release - std::basic_string::empty - std::vector::empty Reviewers: alexfh, hokein, aaron.ballman, ilya-biryukov Reviewed By: aaron.ballman Subscribers: jbcoe, xazax.hun, cfe-commits Tags: #clang-tools-extra Differential Revision: https://reviews.llvm.org/D45891 Patch by khuttun (Kalle Huttunen) llvm-svn: 330772
* [X86][AArch64][NFC] Add tests for masked merge unfolding with %y = constRoman Lebedev2018-04-242-0/+149
| | | | | | | | The fold was added in D45733. This appears to be a regression. llvm-svn: 330771
* [Driver] Android triples are not aliases for other triples.Dan Albert2018-04-242-50/+111
| | | | | | | | | | | | | | | | Summary: Android targets should never use tools/libraries for non-Android targets or vice versa. Reviewers: srhines, george.burgess.iv, eugenis Reviewed By: eugenis Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D45597 llvm-svn: 330770
* [CaptureTracking] Fixup const correctness of DomTree arg (NFC)Daniel Neilson2018-04-242-4/+4
| | | | | | | | | Summary: The PointerMayBeCapturedBefore function's DomTree arg should be const instead of non-const. There are no non-const uses of it in the function. llvm-svn: 330769
* [InstCombine] move tests for select with bit-test of condition; NFCSanjay Patel2018-04-244-441/+444
| | | | | | | | | | | | | | | | | | These are all but 1 of the select-of-constant tests that appear to be transformed within foldSelectICmpAnd() and the block above it predicated by decomposeBitTestICmp(). As discussed in D45862 (and can be seen in several tests here), we probably want to stop doing those transforms because they can increase the instruction count without benefitting other passes or codegen. The 1 test not included here is a urem test where the bit hackery allows us to remove a urem. To preserve killing that urem, we should do some stronger known-bits analysis or pattern matching of 'urem x, (select-of-pow2-constants)'. llvm-svn: 330768
* AMDGPU/GlobalISel: Add support for amdgpu_ps calling conventionTom Stellard2018-04-242-14/+65
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45837 llvm-svn: 330767
* [analyzer] Add support for the note diagnostic pieces to plist output format.Artem Dergachev2018-04-242-32/+127
| | | | | | | | | | | | | | | | | Note diagnostic pieces are an additional way of highlighting code sections to the user. They aren't part of the normal path diagnostic sequence. They can also be attached to path-insensitive reports. Notes are already supported by the text output and scan-build. Expanding our machine-readable plist output format to be able to represent notes opens up the possibility for various analyzer GUIs to pick them up. Patch by Umann Kristóf! Differential Revision: https://reviews.llvm.org/D45407 llvm-svn: 330766
* Remove 'noexcept's that do not match between header and source file.Richard Smith2018-04-241-3/+3
| | | | | | This code is ill-formed, but under -fno-exceptions compilers generally accept it (at least, prior to C++17). This allows this code to be built by Clang in C++17 mode. llvm-svn: 330765
* [wasm] Fix uninitialized memory introduced in r330749.Chandler Carruth2018-04-241-1/+1
| | | | | | | Found with MSan. This was causing all the WASM MC tests to fail about 10% of the time. llvm-svn: 330764
* [bugpoint] Fix crash when testing for miscompilation.Rafael Espindola2018-04-244-12/+15
| | | | | | | | | | | Method BugDriver::performFinalCleanups(...) would delete Module object it worked on, which was also deleted by its caller (e.g. TestCodeGenerator(...)). Changed the code to avoid double delete and make Module ownership slightly clearer. Patch by Andrzej Janik. llvm-svn: 330763
* [Support] fix countLeadingZeros for types shorter than intSam McCall2018-04-241-2/+2
| | | | llvm-svn: 330762
* [cmake] Fix libc++ detectionShoaib Meenai2018-04-241-2/+4
| | | | | | | | | | | -stdlib=libc++ is added to both the compilation and the link flags, but the logic for adding it was only checking if it was supported during compilation and not linking. This could lead to false positives, for example when using clang with libstdc++ (where the compiler would support -stdlib=libc++ but then linking would fail because of libc++ actually being unavailable). llvm-svn: 330761
* [X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.Simon Pilgrim2018-04-241-27/+1
| | | | llvm-svn: 330760
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