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* [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.David Green2019-09-0324-2650/+2081
| | | | | | | | | | | | Arm 8.1-M adds a number of related CSEL instructions, including CSINC, CSNEG and CSINV. These choose between two values given the content in CPSR and a condition, performing an increment, negation or inverse of the false value. This adds some selection for them, either from constant values or patterns. It does not include CSEL directly, which is currently not always making code better. It is still useful, but we will have to check more carefully where it should and shouldn't be used. Code by Ranjeet Singh and Simon Tatham, with some modifications from me. Differential revision: https://reviews.llvm.org/D66483 llvm-svn: 370739
* [ARM] Add csel tests. NFCDavid Green2019-09-031-0/+390
| | | | llvm-svn: 370738
* Added fixit notes for -Wfinal-dtor-non-final-classDavid Bolvansky2019-09-032-4/+11
| | | | llvm-svn: 370737
* [mips] Switch to the `.text` section after emitting asm file preambleSimon Atanasyan2019-09-032-0/+5
| | | | | | | | | | | | | | | | | | | | Now the last `.section` directive in the MIPS asm file preamble is the `.section .mdebug.abi`. If assembler code injected for example by the LLVM `module asm` or the C ` __asm` directives do not contain explicit switching to the `.text` section it goes to the `.mdebug.abi` section. It might be unexpected to the user and in fact for example breaks building some existing code like FreeBSD libc [1]. The patch forces switching to the `.text` section after emitting MIPS assembler file preamble. [1] https://bugs.llvm.org/show_bug.cgi?id=43119 Fix PR43119. Differential Revision: https://reviews.llvm.org/D67014 llvm-svn: 370735
* [lldb] Test 'frame select -r' and fix that INT32_MIN breaks the option parserRaphael Isemann2019-09-034-16/+72
| | | | llvm-svn: 370734
* [lldb][NFC] Test 'command delete'Raphael Isemann2019-09-031-0/+17
| | | | llvm-svn: 370733
* [ARM] Fix MVE ldst offset rangesDavid Green2019-09-033-83/+50
| | | | | | | | | | | | | | | We were using isShiftedInt<7, Shift>(RHSC) to detect the ranges of offsets to fold into MVE loads/stores. The instructions actually take a 7 bit unsigned integer which is either added or subtracted. So something more like isShiftedUInt<7, Shift>(abs(RHSC)). Instead I've changes this to use the isScaledConstantInRange method, same as in SelectT2AddrModeImm7Offset used by pre/post inc, which seemed to already be getting this correct. Differential revision: https://reviews.llvm.org/D66997 llvm-svn: 370731
* [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodingsOliver Stannard2019-09-032-25/+207
| | | | | | | | | | | | | | | | Decoding of VMSR doesn't diagnose some unpredictable encodings, as the unpredictable bits are not correctly set. Diff-reduce this instruction's internals WRT VMRS so I can see the differences better. Mostly this is s/src/Rt/g. Fill in the "should-be-(0)" bits. Designate the Unpredictable{} bits for both VMRS and VMSR. Patch by Mark Murray! Differential revision: https://reviews.llvm.org/D66938 llvm-svn: 370729
* Bug fix on function epilog optimization (ARM backend)Oliver Stannard2019-09-032-2/+16
| | | | | | | | | | | | | | | To save a 'add sp,#val' instruction by adding registers to the final pop instruction, the first register transferred by this pop instruction need to be found. If the function to be optimized has a non-void return value, the operand list contains r0 (implicit) which prevents the optimization to take place. Therefore implicit register references should be skipped in the search loop, because this registers are never popped from the stack. Patch by Rainer Herbertz (rOptimizer)! Differential revision: https://reviews.llvm.org/D66730 llvm-svn: 370728
* [ARM] More MVE load/store tests for offsets around the negative limit. NFCDavid Green2019-09-033-0/+1264
| | | | llvm-svn: 370726
* [lldb][NFC] Test that enabling all log options doesn't crash anythingRaphael Isemann2019-09-031-0/+11
| | | | llvm-svn: 370724
* [LV] Fix miscompiles by adding non-header PHI nodes to AllowedExitBjorn Pettersson2019-09-033-93/+24
| | | | | | | | | | | | | | | | | | | | | | | Summary: Fold-tail currently supports reduction last-vector-value live-out's, but has yet to support last-scalar-value live-outs, including non-header phi's. As it relies on AllowedExit in order to detect them and bail out we need to add the non-header PHI nodes to AllowedExit, otherwise we end up with miscompiles. Solves https://bugs.llvm.org/show_bug.cgi?id=43166 Reviewers: fhahn, Ayal Reviewed By: fhahn, Ayal Subscribers: anna, hiraditya, rkruppe, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67074 llvm-svn: 370721
* [LV] Precommit test case showing miscompile from PR43166. NFCBjorn Pettersson2019-09-031-0/+235
| | | | | | | | | | | | | | | | Summary: Precommit test case showing miscompile from PR43166. Reviewers: fhahn, Ayal Reviewed By: fhahn Subscribers: rkruppe, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67072 llvm-svn: 370720
* [lldb][NFC] Remove unnecessary constructors from invalid-args testsRaphael Isemann2019-09-033-9/+0
| | | | llvm-svn: 370719
* [lldb][NFC] Simplify script_alias testRaphael Isemann2019-09-031-4/+1
| | | | llvm-svn: 370718
* [lldb][NFC] Also test unaliasing in nested_alias testRaphael Isemann2019-09-031-0/+9
| | | | llvm-svn: 370717
* [ARM NEON] Avoid duplicated decarationsDiogo N. Sampaio2019-09-031-3/+22
| | | | | | | | | | | | | | | | | | | | | | Summary: The declaration of arm neon intrinsics that are "big endian safe" print the same code for big and small endian targets. This patch avoids duplicates by checking if an intrinsic is safe to have a single definition. (decreases header 11k lines out of 73k). Reviewers: t.p.northover, ostannard, labrinea Reviewed By: ostannard Subscribers: kristof.beyls, cfe-commits, olista01 Tags: #clang Differential Revision: https://reviews.llvm.org/D66588 llvm-svn: 370716
* [lldb] Test 'command' commands and fix the found crashesRaphael Isemann2019-09-032-0/+71
| | | | llvm-svn: 370712
* [LV] Tail-folding, runtime scev checksSjoerd Meijer2019-09-031-2/+2
| | | | | | | | | Now that we allow tail-folding, not only when we optimise for size, make sure we do not run in this assert. Differential revision: https://reviews.llvm.org/D66932 llvm-svn: 370711
* [RISCV] Correct Logic around ilp32e macrosSam Elliott2019-09-031-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCC seperates the `__riscv_float_abi_*` macros and the `__riscv_abi_rve` macro. If the chosen abi is ilp32e, `gcc -march=rv32i -mabi=ilp32i -E -dM` shows that both `__riscv_float_abi_soft` and `__riscv_abi_rve` are set. This patch corrects the compiler logic around these defines. At the moment, this patch will not change clang's behaviour, because we do not accept the `ilp32e` abi yet. Reviewers: luismarques, asb Reviewed By: luismarques Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66591 llvm-svn: 370709
* [LV] Tail-folding with runtime memory checksSjoerd Meijer2019-09-031-1/+4
| | | | | | | | | The loop vectorizer was running in an assert when it tried to fold the tail and had to emit runtime memory disambiguation checks. Differential revision: https://reviews.llvm.org/D66803 llvm-svn: 370707
* [lldb][NFC] Unify log files in commands/log/basicRaphael Isemann2019-09-031-9/+7
| | | | llvm-svn: 370706
* [MachinePipeliner] Add a way to unit-test the schedule emitterJames Molloy2019-09-036-0/+298
| | | | | | | | | | | | | | | | | | Emitting a schedule is really hard. There are lots of corner cases to take care of; in fact, of the 60+ SWP-specific testcases in the Hexagon backend most of those are testing codegen rather than the schedule creation itself. One issue is that to test an emission corner case we must craft an input such that the generated schedule uses that corner case; sometimes this is very hard and convolutes testcases. Other times it is impossible but we want to test it anyway. This patch adds a simple test pass that will consume a module containing a loop and generate pipelined code from it. We use post-instr-symbols as a way to annotate instructions with the stage and cycle that we want to schedule them at. We also provide a flag that causes the MachinePipeliner to generate these annotations instead of actually emitting code; this allows us to generate an input testcase with: llc < %s -stop-after=pipeliner -pipeliner-annotate-for-testing -o test.mir And run the emission in isolation with: llc < test.mir -run-pass=modulo-schedule-test llvm-svn: 370705
* [ARM] Select vmlaSam Tebbs2019-09-032-0/+95
| | | | | | | | This patch adds vmla selection. Differential revision: https://reviews.llvm.org/D66297 llvm-svn: 370704
* [lldb][NFC] Remove setup boilerplate from types/ testsRaphael Isemann2019-09-037-52/+1
| | | | | | This code doesn't seem to be necessary anymore. llvm-svn: 370702
* [X86] Simplify the setOperationAction handling for fp_to_uint by improving ↵Craig Topper2019-09-032-19/+22
| | | | | | | | | | | | | | | | the Custom handler a bit. This merges the 32-bit and 64-bit mode code to just use Custom for both i32 and i64. We already had most of the handling in the custom handling due to the AVX512 having legal fp_to_uint. Just needed to add the i32->i64 promotion handling. Refactor the fp_to_uint code in the custom handler to simplify the number of times we check things. Tweak cost model tables to match the default handling we were getting due to Expand before. llvm-svn: 370700
* [X86] Don't use Expand for i32 fp_to_uint on SSE1/2 targets on 32-bit target.Craig Topper2019-09-032-139/+63
| | | | | | | | Use Custom lowering instead. Fall back to default expansion only when the scalar FP type belongs in an XMM register. This improves lowering for i32 to fp80, and also i32 to double on SSE1 only. llvm-svn: 370699
* [X86] Add an exhaustive test for i32 fptosi/fptoui across different triples ↵Craig Topper2019-09-031-0/+1094
| | | | | | and features. llvm-svn: 370698
* [LegalizeDAG] Pass DAG to two calls to SDNode::dump in debug prints so that ↵Craig Topper2019-09-031-2/+2
| | | | | | | | | they will print target specific nodes correctly. The dump methods can only print target node names correctly if they can get access to the TLI object. llvm-svn: 370694
* [X86] Custom promote i32->f80 uint_to_fp on AVX512 64-bit targets.Craig Topper2019-09-032-24/+13
| | | | | | | Reuse the same code to promote all i32 uint_to_fp on 64-bit targets to simplify the X86ISelLowering constructor. llvm-svn: 370693
* [x86] Fix bugs of some intrinsic functions in CLANG : _mm512_stream_ps, ↵Pengfei Wang2019-09-032-3/+20
| | | | | | | | | | | | | | | | _mm512_stream_pd, _mm512_stream_si512 Reviewers: craig.topper, pengfei, LuoYuanke, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Patch by Bing Yu (yubing) Differential Revision: https://reviews.llvm.org/D66786 llvm-svn: 370691
* Rename -Wc++20-designator to -Wc++2a-designator for consistency and addRichard Smith2019-09-022-11/+12
| | | | | | some test coverage for the flag. llvm-svn: 370689
* Split -Wreorder into different warnings for reordering a constructorRichard Smith2019-09-023-7/+9
| | | | | | mem-initializer list and for reordering a designated initializer list. llvm-svn: 370688
* [CostModel][X86] Add scalar sext/zext cost testsSimon Pilgrim2019-09-021-0/+158
| | | | llvm-svn: 370684
* [X86] Enable fp128 as a legal type with SSE1 rather than with MMX.Craig Topper2019-09-028-377/+175
| | | | | | | | | | | | | | | | FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
* [ARM] MVE predicate bitcast test and VPSEL adjustment. NFCDavid Green2019-09-022-20/+193
| | | | llvm-svn: 370678
* [Wdocumentation] fixes an assertion failure with typedefed function and ↵Dmitri Gribenko2019-09-023-0/+47
| | | | | | | | | | | | | | | | | | | | | block pointer Summary: The assertion happens when compiling with -Wdocumentation with variable declaration to a typedefed function pointer. I not too familiar with the ObjC syntax but first two tests assert without this patch. Fixes https://bugs.llvm.org/show_bug.cgi?id=42844 Reviewers: gribozavr Reviewed By: gribozavr Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66706 llvm-svn: 370677
* [ARM] Use MQPR not QPR for MVE registersDavid Green2019-09-024-96/+211
| | | | | | | | | We should be using MQPR, and if we don't we can get COPYs and PHIs created for QPR. These get folded into instructions, failing verification checks. Differential revision: https://reviews.llvm.org/D66214 llvm-svn: 370676
* [TargetLowering][PS4] Add sincos(f) lib functions when target is PS4Robert Lougher2019-09-022-0/+32
| | | | | | | | | PS4 supports sincosf and sincos. Adding the library functions enables the sin(f)+cos(f) -> sincos(f) optimization. Differential Revision: https://reviews.llvm.org/D67009 llvm-svn: 370675
* [SystemZ] Support constrained fpto[su]i intrinsicsUlrich Weigand2019-09-0212-16/+547
| | | | | | | | | | | Now that constrained fpto[su]i intrinsic are available, add codegen support to the SystemZ backend. In addition to pure back-end changes, I've also needed to add the strict_fp_to_[su]int and any_fp_to_[su]int pattern fragments in the obvious way. llvm-svn: 370674
* [SVE][Inline-Asm] Support for SVE asm operandsKerry McLaughlin2019-09-028-9/+150
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Adds the following inline asm constraints for SVE: - w: SVE vector register with full range, Z0 to Z31 - x: Restricted to registers Z0 to Z15 inclusive. - y: Restricted to registers Z0 to Z7 inclusive. This change also adds the "z" modifier to interpret a register as an SVE register. Not all of the bitconvert patterns added by this patch are used, but they have been included here for completeness. Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, rengolin, cameron.mcinally, greened Reviewed By: sdesmalen Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66302 llvm-svn: 370673
* ThinLTO: Document the option BOOTSTRAP_LLVM_ENABLE_LTOSylvestre Ledru2019-09-021-0/+4
| | | | llvm-svn: 370671
* [X86] getPMOVMSKB - add MVT::v64i8 handling and remove from ↵Simon Pilgrim2019-09-021-11/+12
| | | | | | combineBitcastvxi1. NFCI. llvm-svn: 370670
* Recommit r370661 "[llvm-nm] - Add a test case for case when we dump a symbol ↵George Rimar2019-09-022-4/+30
| | | | | | | | | | | | | | | | | | | that belongs to a section with a broken sh_name." Fix: add a 'consumeError()' call to ObjectFile.cpp. This error was never checked. Original commit message: It adds a test case for a problem fixed by D66976 <https://reviews.llvm.org/D66976>. It was introduced by me in D66089 <https://reviews.llvm.org/D66089>. The error reported was never consumed because of a wrong variable name used, so it could fail when LLVM_ENABLE_ABI_BREAKING_CHECKS is used. Differential revision: https://reviews.llvm.org/D67002 llvm-svn: 370669
* [DAGCombiner] try to form test+set out of shift+mask patternsSanjay Patel2019-09-023-32/+109
| | | | | | | | | | | | | | | | | | | | | The motivating bugs are: https://bugs.llvm.org/show_bug.cgi?id=41340 https://bugs.llvm.org/show_bug.cgi?id=42697 As discussed there, we could view this as a failure of IR canonicalization, but then we would need to implement a backend fixup with target overrides to get this right in all cases. Instead, we can just view this as a codegen opportunity. It's not even clear for x86 exactly when we should favor test+set; some CPUs have better theoretical throughput for the ALU ops than bt/test. This patch is made more complicated than I expected because there's an early DAGCombine for 'and' that can change types of the intermediate ops via trunc+anyext. Differential Revision: https://reviews.llvm.org/D66687 llvm-svn: 370668
* Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in ↵Jay Foad2019-09-025-28/+27
| | | | | | | | | | | | | | | | | | | SI_PC_ADD_REL_OFFSET is 0" Summary: D61491 caused us to use relocs when they're not strictly necessary, to refer to symbols in the text section. This is a pessimization and it's a problem for some loaders that don't support relocs yet. Reviewers: nhaehnle, arsenm, tpr Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65813 llvm-svn: 370667
* [AMDGPU][MC][GFX10] Corrected constant bus checks to exclude nullDmitry Preobrazhensky2019-09-022-3/+12
| | | | | | | | | | See AMD SWDEV-157286 Reviewers: atamazov, arsenm Differential Revision: https://reviews.llvm.org/D65229 llvm-svn: 370665
* [FileCheck] Make NumericVariable ctor explicitThomas Preud'homme2019-09-021-2/+2
| | | | | | | | | | | | | | | | Summary: Make FileCheckNumericVariable constructor explicit to avoid implicit conversions from StringRef. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66640 llvm-svn: 370664
* [FileCheck] Forbid using var defined on same lineThomas Preud'homme2019-09-025-110/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Commit r366897 introduced the possibility to set a variable from an expression, such as [[#VAR2:VAR1+3]]. While introducing this feature, it introduced extra logic to allow using such a variable on the same line later on. Unfortunately that extra logic is flawed as it relies on a mapping from variable to expression defining it when the mapping is from variable definition to expression. This flaw causes among other issues PR42896. This commit avoids the problem by forbidding all use of a variable defined on the same line, and removes the now useless logic. Redesign will be done in a later commit because it will require some amount of refactoring first for the solution to be clean. One example is the need for some sort of transaction mechanism to set a variable temporarily and from an expression and rollback if the CHECK pattern does not match so that diagnostics show the right variable values. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya Tags: #llvm Differential Revision: https://reviews.llvm.org/D66141 llvm-svn: 370663
* Revert r370661 "[llvm-nm] - Add a test case for case when we dump a symbol ↵George Rimar2019-09-021-27/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | that belongs to a section with a broken sh_name" It broke BB: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/16955/steps/test/logs/stdio Expected<T> must be checked before access or destruction. Unchecked Expected<T> contained error: a section [index 1] has an invalid sh_name (0xffff) offset which goes past the end of the section name string tableStack dump: 0. Program arguments: /srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm /srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/test/tools/llvm-nm/Output/format-sysv-section.test.tmp2.o --format=sysv #0 0x00000000008af7c4 PrintStackTraceSignalHandler(void*) (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x8af7c4) #1 0x00000000008ad8be llvm::sys::RunSignalHandlers() (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x8ad8be) #2 0x00000000008afbd8 SignalHandler(int) (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x8afbd8) #3 0x00007f0a6b989730 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12730) #4 0x00007f0a6b48d7bb raise (/lib/x86_64-linux-gnu/libc.so.6+0x377bb) #5 0x00007f0a6b478535 abort (/lib/x86_64-linux-gnu/libc.so.6+0x22535) #6 0x000000000042004b llvm::Expected<llvm::StringRef>::fatalUncheckedExpected() const (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x42004b) #7 0x00000000008367f5 (/sv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x8367f5) #8 0x0000000000817b80 llvm::object::IRObjectFile::findBitcodeInObject(llvm::object::ObjectFile const&) (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x817b80) #9 0x0000000000838416 llvm::object::SymbolicFile::createSymbolicFile(llvm::MemoryBufferRef, llvm::file_magic, llvm::LLVMContext*) (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x838416) #10 0x00000000007f36cb llvm::object::createBinary(llvm::MemoryBufferRef, llvm::LLVMContext*) (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x7f36cb) #11 0x0000000000413123 dumpSymbolNamesFromFile(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >&) (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x413123) #12 0x0000000000412e38 main (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x412e38) #13 0x00007f0a6b47a09b __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2409b) #14 0x00000000004120da _start (/srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/llvm-nm+0x4120da) FileCheck error: '-' is empty. FileCheck command line: /srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.obj/bin/FileCheck /srv/llvm-buildbot-srcatch/llvm-build-dir/clang-x86_64-debian-fast/llvm.src/test/tools/llvm-nm/format-sysv-section.test --check-prefix=ERR -- llvm-svn: 370662
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