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* [StringRef] Test all default characters in unit testJonas Devlieghere2019-12-111-0/+4
| | | | | The default characters for trim, ltrim and rtrim are " \t\n\v\f\r" but only spaces were tested. Test that the others are trimmed as well.
* [SDAG] remove use restriction in isNegatibleForFree() when called from ↵Sanjay Patel2019-12-116-20/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | getNegatedExpression() This is an alternate fix for the bug discussed in D70595. This also includes minimal tests for other in-tree targets to show the problem more generally. We check the number of uses as a predicate for whether some value is free to negate, but that use count can change as we rewrite the expression in getNegatedExpression(). So something that was marked free to negate during the cost evaluation phase becomes not free to negate during the rewrite phase (or the inverse - something that was not free becomes free). This can lead to a crash/assert because we expect that everything in an expression that is negatible to be handled in the corresponding code within getNegatedExpression(). This patch skips the use check during the rewrite phase. So we determine that some expression isNegatibleForFree (identically to without this patch), but during the rewrite, don't rely on use counts to decide how to create the optimal expression. Differential Revision: https://reviews.llvm.org/D70975
* [OPENMP50]Fix capturing of if condition in target parallel for simdAlexey Bataev2019-12-112-5/+9
| | | | | | | | directive. Fixed capturing of the if condition if no modifer was specified in this condition. Previously could capture it only in outer region and it could lead to a compiler crash.
* [profile] Avoid allocating a page on the stack, NFCVedant Kumar2019-12-114-14/+33
| | | | | | | | | | | | | | | | | | | | | When writing out a profile, avoid allocating a page on the stack for the purpose of writing out zeroes, as some embedded environments do not have enough stack space to accomodate this. Instead, use a small, fixed-size zero buffer that can be written repeatedly. For a synthetic file with >100,000 functions, I did not measure a significant difference in profile write times. We are removing a page-length zero-fill `memset()` in favor of several smaller buffered `fwrite()` calls: in practice, I am not sure there is much of a difference. The performance impact is only expected to affect the continuous sync mode (%c) -- zero padding is less than 8 bytes in all other cases. rdar://57810014 Differential Revision: https://reviews.llvm.org/D71323
* [profile] Delete stale profiles in test/profile/instrprof-value-prof.test, NFCVedant Kumar2019-12-111-0/+1
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* [profile] Delete stale profile in test/profile/instrprof-set-filename.c, NFCVedant Kumar2019-12-111-0/+2
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* [VFS] Extend virtual working directory testJonas Devlieghere2019-12-111-0/+25
| | | | | Extend the virtual working directory test with a few edge cases that are not currently tested.
* [OPENMP50]Add if clause in teams distribute simd directive.Alexey Bataev2019-12-116-21/+186
| | | | | | According to OpenMP 5.0, if clause can be used in for simd directive. If condition in the if clause if false, the non-vectorized version of the loop must be executed.
* Remove TypeValidators (NFC in terms of the testsuite)Adrian Prantl2019-12-1126-635/+14
| | | | | | | | This is a half-implemented feature that as far as we can tell was never used by anything since its original inclusion in 2014. This patch removes it to make remaining the code easier to understand. Differential Revision: https://reviews.llvm.org/D71310
* [ELF][AArch64] Rename --force-bti to -z force-bti and --pac-plt to -z pac-pltFangrui Song2019-12-117-37/+34
| | | | | | | | | | | | | | | | | | | Summary: The original design used --foo but the upstream complained that ELF only options should be -z foo. See https://sourceware.org/ml/binutils/2019-04/msg00151.html https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=8bf6d176b0a442a8091d338d4af971591d19922c made the rename. Our --force-bti and --pac-plt implement the same functionality, so it seems wise to be consistent with GNU ld. Reviewed By: peter.smith Subscribers: emaste, arichardson, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71327
* update TestThreadStepOut.py to expect correct source line on arm64.Jason Molenda2019-12-112-3/+3
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* [DA] Improve dump to show source and sink of the dependenceBardia Mahjour2019-12-112-10/+57
| | | | | | | | | | | | | | | | | | | | Summary: The current da printer shows the dependence without indicating which instructions are being considered as the src vs dst. It also silently ignores call instructions, despite the fact that they create confused dependence edges to other memory instructions. This patch addresses these two issues plus a couple of minor non-functional improvements. Authored By: bmahjour Reviewer: dmgreen, fhahn, philip.pfaffe, chandlerc Reviewed By: dmgreen, fhahn Tags: #llvm Differential Revision: https://reviews.llvm.org/D71088
* Don't run expect based tests remotely.Jason Molenda2019-12-112-2/+2
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* [AArch64] Skip debug ops with regsOverlap in AArch64 LD/ST opt.Florian Hahn2019-12-112-1/+50
| | | | This fixes a crash when debug instructions are in between 2 stores.
* [SystemZ] Add llvm.minimum / llvm.maximum testsUlrich Weigand2019-12-112-32/+148
| | | | | The backend already supports the @llvm.minimum and @llvm.maximum intrinsics, but we had no test cases for those. Add tests.
* [X86] Erase dead LEA instruction after converting it to MOV in ↵Craig Topper2019-12-113-2/+3
| | | | FixupLEAPass::processInstrForSlow3OpLEA.
* [TableGen] Remove unused target intrinsic generation logicReid Kleckner2019-12-117-75/+20
| | | | | | | | | | | | AMDGPU was the last in tree target to use this tablegen mode. I plan to split up the global intrinsic enum similar to the way that clang diagnostics are split up today. I don't plan to build on this mode. Reviewers: arsenm, echristo, efriedma Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D71318
* [SystemZ] Fix 128-bit strict FMA expansion pre-z14Ulrich Weigand2019-12-114-6/+127
| | | | | | | | | | | | | Before z14, we did not have any FMA instruction for 128-bit floating-point, so the @llvm.fma.f128 intrinsic needs to be expanded to a libcall on those platforms. This worked correctly for regular FMA, but was implemented incorrectly for the strict version. This was not noticed because we did not have test coverage for this case. This patch fixes that incorrect expansion and adds the missing test cases.
* [Loop] Add isRotated method to Loop class.Kit Barton2019-12-113-1/+63
| | | | | | | | | | | | | | | | | | Summary: This patch adds a method to determine if a loop is in rotated form (the latch is an exiting block). It also modifies the getLoopGuardBranch method to use this new method. This method can also be used in Loopfusion. Once this patch lands I will make the corresponding changes there. Reviewers: jdoerfert, Meinersbur, dmgreen, etiotto, Whitney, fhahn, hfinkel Reviewed By: Meinersbur Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65958
* [Support] Add TimeTraceScope constructor without detail argRussell Gallop2019-12-118-12/+17
| | | | | | | This simplifies code where no extra details are required Also don't write out detail when it is empty. Differential Revision: https://reviews.llvm.org/D71347
* [ARM][NFC] Change test to use CHECK-NEXTDiogo Sampaio2019-12-111-91/+93
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* Verifier: Check frame-pointer attribute valuesMatt Arsenault2019-12-114-0/+34
| | | | | | There are a few places that check specific string attributes have particular values, and assert if they are something else. The verifier should catch these kinds of cases.
* [Analyzer] Iterator Checkers: Replace `UnknownVal` in comparison result by a ↵Adam Balogh2019-12-113-8/+17
| | | | | | | | | | | | | conjured value Sometimes the return value of a comparison operator call is `UnkownVal`. Since no assumptions can be made on `UnknownVal`, this leeds to keeping impossible execution paths in the exploded graph resulting in poor performance and false positives. To overcome this we replace unknown results of iterator comparisons by conjured symbols. Differential Revision: https://reviews.llvm.org/D70244
* AMDGPU: Fix copy-pasted test name errorMatt Arsenault2019-12-111-2/+2
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* [LLD][ELF][AArch64][ARM] When errata patching, round thunk size to 4KiB.Peter Smith2019-12-114-44/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some edge cases such as Chromium compiled with full instrumentation we have a .text section over twice the size of the maximum branch range and the instrumented code generation containing many examples of the erratum sequence. The combination of Thunks and many erratum sequences causes finalizeAddressDependentContent() to not converge. We end up with: start - Thunk Creation (disturbs addresses after thunks, creating more patches) - Patch Creation (disturbs addresses after patches, creating more thunks) - goto start In most images with few thunks and patches the mutual disturbance does not cause convergence problems. As the .text size and number of patches go up the risk increases. A way to prevent the thunk creation from interfering with patch creation is to round up the size of the thunks to a 4KiB boundary when the erratum patch is enabled. As the erratum sequence only triggers when an instruction sequence starts at 0xff8 or 0xffc modulo (4 KiB) by making the thunks not affect addresses modulo (4 KiB) we prevent thunks from interfering with the patch. The patches themselves could be aggregated in the same way that Thunks are within ThunkSections and we could round up the size in the same way. This would reduce the number of patches created in a .text section size > 128 MiB but would not likely help convergence problems. Differential Revision: https://reviews.llvm.org/D71281 fixes (remaining part of) pr44071, other part in D71242
* [LLD][ELF][AArch64][ARM] Add missing classof to patch sections.Peter Smith2019-12-113-0/+95
| | | | | | | | | | | | | The code to insert patch section merges them with a comparison function that uses logic of the form: return (isa<PatchSection>(a) && !isa<PatchSection>(b)); If the PatchSections don't implement classof this check fails if b is also a SyntheticSection. This can result in the patches being out of range if the SyntheticSection is big, for example a ThunkSection with lots of thunks. Differential Revision: https://reviews.llvm.org/D71242 fixes (part of) pr44071
* [lldb] Don't search the metadata map three times when retrieving metadataRaphael Isemann2019-12-113-8/+4
| | | | | | HasMetadata checks if our metadata map knows the given object. GetMetadata also does this check and then does another search to actually retrieve the value. This can all just be one lookup.
* Revert "[AArch64][SVE] Implement intrinsics for non-temporal loads & stores"Kerry McLaughlin2019-12-117-311/+3
| | | | | | | | This reverts commit 3f5bf35f868d1e33cd02a5825d33ed4675be8cb1 as it was causing build failures in llvm-clang-x86_64-expensive-checks: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-debian/builds/392 http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-ubuntu/builds/1045
* [AArch64] Teach Load/Store optimizier to rename store operands for pairing.Florian Hahn2019-12-117-52/+824
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases, we can rename a store operand, in order to enable pairing of stores. For store pairs, that cannot be merged because the first tored register is defined in between the second store, we try to find suitable rename register. First, we check if we can rename the given register: 1. The first store register must be killed at the store, which means we do not have to rename instructions after the first store. 2. We scan backwards from the first store, to find the definition of the stored register and check all uses in between are renamable. Along they way, we collect the minimal register classes of the uses for overlapping (sub/super)registers. Second, we try to find an available register from the minimal physical register class of the original register. A suitable register must not be 1. defined before FirstMI 2. between the previous definition of the register to rename 3. a callee saved register. We use KILL flags to clear defined registers while scanning from the beginning to the end of the block. This triggers quite often, here are the top changes for MultiSource, SPEC2000, SPEC2006 compiled with -O3 for iOS: Metric: aarch64-ldst-opt.NumPairCreated Program base patch diff test-suite...nch/fourinarow/fourinarow.test 2.00 39.00 1850.0% test-suite...s/ASC_Sequoia/IRSmk/IRSmk.test 46.00 80.00 73.9% test-suite...chmarks/Olden/power/power.test 70.00 96.00 37.1% test-suite...cations/hexxagon/hexxagon.test 29.00 39.00 34.5% test-suite...nchmarks/McCat/05-eks/eks.test 100.00 132.00 32.0% test-suite.../Trimaran/enc-rc4/enc-rc4.test 46.00 59.00 28.3% test-suite...T2006/473.astar/473.astar.test 160.00 200.00 25.0% test-suite.../Trimaran/enc-md5/enc-md5.test 8.00 10.00 25.0% test-suite...telecomm-gsm/telecomm-gsm.test 113.00 139.00 23.0% test-suite...ediabench/gsm/toast/toast.test 113.00 139.00 23.0% test-suite...Source/Benchmarks/sim/sim.test 91.00 111.00 22.0% test-suite...C/CFP2000/179.art/179.art.test 41.00 49.00 19.5% test-suite...peg2/mpeg2dec/mpeg2decode.test 245.00 279.00 13.9% test-suite...marks/Olden/health/health.test 16.00 18.00 12.5% test-suite...ks/Prolangs-C/cdecl/cdecl.test 90.00 101.00 12.2% test-suite...fice-ispell/office-ispell.test 91.00 100.00 9.9% test-suite...oxyApps-C/miniGMG/miniGMG.test 430.00 465.00 8.1% test-suite...lowfish/security-blowfish.test 39.00 42.00 7.7% test-suite.../Applications/spiff/spiff.test 42.00 45.00 7.1% test-suite...arks/mafft/pairlocalalign.test 2473.00 2646.00 7.0% test-suite.../VersaBench/ecbdes/ecbdes.test 29.00 31.00 6.9% test-suite...nch/beamformer/beamformer.test 220.00 235.00 6.8% test-suite...CFP2000/177.mesa/177.mesa.test 2110.00 2252.00 6.7% test-suite...ve-susan/automotive-susan.test 109.00 116.00 6.4% test-suite...s-C/unix-smail/unix-smail.test 65.00 69.00 6.2% test-suite...CI_Purple/SMG2000/smg2000.test 1194.00 1265.00 5.9% test-suite.../Benchmarks/nbench/nbench.test 472.00 500.00 5.9% test-suite...oxyApps-C/miniAMR/miniAMR.test 248.00 262.00 5.6% test-suite...quoia/CrystalMk/CrystalMk.test 18.00 19.00 5.6% test-suite...rks/tramp3d-v4/tramp3d-v4.test 7331.00 7710.00 5.2% test-suite.../Benchmarks/Bullet/bullet.test 5651.00 5938.00 5.1% test-suite...ternal/HMMER/hmmcalibrate.test 750.00 788.00 5.1% test-suite...T2006/456.hmmer/456.hmmer.test 764.00 802.00 5.0% test-suite...ications/JM/ldecod/ldecod.test 1028.00 1079.00 5.0% test-suite...CFP2006/444.namd/444.namd.test 1368.00 1434.00 4.8% test-suite...marks/7zip/7zip-benchmark.test 4471.00 4685.00 4.8% test-suite...6/464.h264ref/464.h264ref.test 3122.00 3271.00 4.8% test-suite...pplications/oggenc/oggenc.test 1497.00 1565.00 4.5% test-suite...T2000/300.twolf/300.twolf.test 742.00 774.00 4.3% test-suite.../Prolangs-C/loader/loader.test 24.00 25.00 4.2% test-suite...0.perlbench/400.perlbench.test 1983.00 2058.00 3.8% test-suite...ications/JM/lencod/lencod.test 4612.00 4785.00 3.8% test-suite...yApps-C++/PENNANT/PENNANT.test 995.00 1032.00 3.7% test-suite...arks/VersaBench/dbms/dbms.test 54.00 56.00 3.7% Reviewers: efriedma, thegameg, samparker, dmgreen, paquette, evandro Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D70450
* Removing an unused selection field from a diagnostic; NFC.Aaron Ballman2019-12-111-1/+1
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* [test][llvm-dwarfdump] Add missing testing for some --debug-* optionsJames Henderson2019-12-114-0/+271
| | | | | | | | | | | | | | | | | A number of the --debug-* options in llvm-dwarfdump are not particularly well tested. In some cases, the option is only tested as part of testing another feature, or a specific part of the section that the options dump. This change adds four new tests to address some of these holes. It is not aiming to address every hole however. I kept the --debug-line switch test separate to X86/brief.s because the latter only considers the parts of the line table that are affected by verbose printing, thus missing out things like the header and different values for things like the Line, Column etc registers. Reviewed by: JDevlieghere Differential Revision: https://reviews.llvm.org/D71276
* [Alignment][NFC] Introduce Align in IRBuilderGuillaume Chatelet2019-12-113-26/+63
| | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71343
* [DebugInfo] Fix printing of DW_LNS_set_isaJames Henderson2019-12-112-1/+53
| | | | | | | | | | | | | | | | | The Isa register is a uint8_t, but at least on Windows this is internally an unsigned char, which meant that prior to this patch it got formatted as an ASCII character, rather than a decimal number. This patch fixes this by casting it to a uint64_t before printing. I did it this way instead of using a uint8_t formatter because a) it is simpler, and b) it allows us to change the internal type of Isa in the future without this code breaking. I also took the opportunity to test the printing of the other standard opcodes. Reviewed by: probinson Differential Revision: https://reviews.llvm.org/D71274
* [lldb][NFC] Remove dead metadata code in ClangASTSourceProxyRaphael Isemann2019-12-111-12/+0
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* Rollback assumeAligned in MemorySanitizerGuillaume Chatelet2019-12-111-18/+22
| | | | | | | | | | | | Summary: Rollback of parts of D71213. After digging more into the code I think we should leave 0 when creating the instructions (CreateMemcpy, CreateMaskedStore, CreateMaskedLoad). It's probably fine for MemorySanitizer because Alignement is resolved but I'm having a hard time convincing myself it has no impact at all (although tests are passing). Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71332
* [Analyzer] Iterator Modeling: Print Container Data and Iterator Positions ↵Adam Balogh2019-12-112-0/+84
| | | | | | | | | | | | when printing the Program State Debugging the Iterator Modeling checker or any of the iterator checkers is difficult without being able to see the relations between the iterator variables and their abstract positions, as well as the abstract symbols denoting the begin and the end of the container. This patch adds the checker-specific part of the Program State printing to the Iterator Modeling checker.
* [lldb][NFC] Remove ClangExternalASTSourceCommon::g_TotalSizeOfMetadataRaphael Isemann2019-12-111-7/+0
| | | | Turns out this counter is doing literally nothing beside counting.
* [AArch64][SVE] Add DAG combine rules for gather loads and sext/zextAndrzej Warzynski2019-12-119-134/+609
| | | | | | | | | | | | | | | | Summary: These changes allow us to support sign-extending gather loads with the exisiting intrinsics (i.e. @llvm.aarch64.sve.ld1.gather.*). Reviewers: sdesmalen, huntergr, kmclaughlin, efriedma, rengolin, rovka, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential revision: https://reviews.llvm.org/D70812
* [SYCL] Add support for auxiliary triple specification to FrontendAlexey Bader2019-12-113-3/+10
| | | | | | | | | | | | | | | | | Summary: Add host predefined macros to compilation for SYCL device, which is required for pre-processing host specific includes (e.g. system headers). Reviewers: ABataev, jdoerfert Subscribers: ebevhan, Anastasia, cfe-commits, keryell, Naghasan, Fznamznon Tags: #clang Differential Revision: https://reviews.llvm.org/D71286 Signed-off-by: Alexey Bader <alexey.bader@intel.com>
* CodeGen: Allow annotations on globals in non-zero address spaceNicolai Hähnle2019-12-112-5/+17
| | | | | | | | | | | | | | | | | | | | | | Summary: Attribute annotations are recorded in a special global composite variable that points to annotation strings and the annotated objects. As a restriction of the LLVM IR type system, those pointers are all pointers to address space 0, so let's insert an addrspacecast when the annotated global is in a non-0 address space. Since this addrspacecast is only reachable from the global annotations object, this should allow us to represent annotations on all globals regardless of which addrspacecasts are usually legal for the target. Reviewers: rjmccall Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71208
* gn build: Merge afb13afcf22LLVM GN Syncbot2019-12-111-1/+6
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* [ARM][MVE] Factor out an IntrinsicMX multiclass.Simon Tatham2019-12-112-27/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The ACLE intrinsics for MVE contain a lot of pairs of functions with `_m` and `_x` in the name, wrapping a predicated MVE instruction which only partially overwrites its output register. They have the common pattern that the `_m` variant takes an initial argument called 'inactive', of the same type as the return value, supplying the input value of the output register, so that lanes disabled by the predication will be taken from that parameter; the `_x` variant omits that initial argument, and simply sets it to undef. That common pattern is simple enough to wrap into a multiclass, which should save a lot of effort in setting up all the rest of the `_x` variants. In this commit I introduce `multiclass IntrinsicMX` in `arm_mve_defs.td`, and convert existing generation of m/x pairs to use it. This allows me to remove the `PredicatedImmediateVectorShift` multiclass (from D71065) completely, because the new multiclass makes it so much simpler that it's not worth bothering to define it at all. Reviewers: MarkMurrayARM, miyuki Reviewed By: MarkMurrayARM, miyuki Subscribers: kristof.beyls, dmgreen, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71335
* [llvm-readobj][llvm-readelf] - Remove excessive empty lines when reporting ↵Georgii Rymar2019-12-119-129/+94
| | | | | | | | | | errors and warnings. After recent changes it is now seems possible to get rid of printing '\n' before each error and warning. This makes the output cleaner. Differential revision: https://reviews.llvm.org/D71246
* Revert "Reland [AArch64][MachineOutliner] Return address signing for ↵Oliver Stannard2019-12-1112-1275/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | outlined functions" This reverts commit cec2d5c17457722113580251c8a045fa9aca9b1b. Reverting because this is still creating outlined functions with return address signing instructions with mismatches SP values. For example: int *volatile v; void foo(int x) { int a[x]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; } void bar(int x) { int a[x]; v = 0; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; v = &a[0]; } This generates these two outlined functions, both of which modify SP between the paciasp and retaa instructions: $ clang --target=aarch64-arm-none-eabi -march=armv8.3-a -c test2.c -o - -S -Oz -mbranch-protection=pac-ret+leaf ... OUTLINED_FUNCTION_0: // @OUTLINED_FUNCTION_0 .cfi_sections .debug_frame .cfi_startproc // %bb.0: paciasp .cfi_negate_ra_state mov w8, w0 lsl x8, x8, #2 add x8, x8, #15 // =15 mov x9, sp and x8, x8, #0x7fffffff0 sub x8, x9, x8 mov x29, sp mov sp, x8 adrp x9, v retaa ... OUTLINED_FUNCTION_1: // @OUTLINED_FUNCTION_1 .cfi_startproc // %bb.0: paciasp .cfi_negate_ra_state str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] str x8, [x9, :lo12:v] mov sp, x29 retaa
* [TableGen] Add bang-operators !getop and !setop.Simon Tatham2019-12-118-10/+172
| | | | | | | | | | | | | | | | | | | | | | Summary: These allow you to get and set the operator of a dag node, without affecting its list of arguments. `!getop` is slightly fiddly because in many contexts you need its return value to have a static type more specific than 'any record'. It works to say `!cast<BaseClass>(!getop(...))`, but it's cumbersome, so I made `!getop` take an optional type suffix itself, so that can be written as the shorter `!getop<BaseClass>(...)`. Reviewers: hfinkel, nhaehnle Reviewed By: nhaehnle Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71191
* [Analyzer][NFC] Iterator Checkers - Separate iterator modeling and the ↵Adam Balogh2019-12-118-1131/+1429
| | | | | | | | | | actual checkers A monolithic checker class is hard to maintain. This patch splits it up into a modeling part, the three checkers and a debug checker. The common functions are moved into a library. Differential Revision: https://reviews.llvm.org/D70320
* [clang-tidy] Link shared library clangTidyOpenMPModule to library ↵Adam Balogh2019-12-111-0/+1
| | | | | | LLVMFrontendOpenMP Building shared libs was broken, it is fixed now.
* [AArch64][SVE] Implement intrinsics for non-temporal loads & storesKerry McLaughlin2019-12-117-3/+311
| | | | | | | | | | | | | | | | | | | | Summary: Adds the following intrinsics: - llvm.aarch64.sve.ldnt1 - llvm.aarch64.sve.stnt1 This patch creates masked loads and stores with the MONonTemporal flag set when used with the intrinsics above. Reviewers: sdesmalen, paulwalker-arm, dancgr, mgudim, efriedma, rengolin Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71000
* [PowerPC][NFC] add test case for lwa - loop ds form prepczhengsz2019-12-111-0/+73
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* [Clang] Pragma vectorize_width() implies vectorize(enable)Sjoerd Meijer2019-12-113-17/+70
| | | | | | | | | | | | | | | | | | | | | | Let's try this again; this has been reverted/recommited a few times. Last time this got reverted because for this loop: void a() { #pragma clang loop vectorize(disable) for (;;) ; } vectorisation was incorrectly enabled and the vectorize.enable metadata was set due to a logic error. But with this fixed, we now imply vectorisation when: 1) vectorisation is enabled, which means: VectorizeWidth > 1, 2) and don't want to add it when it is disabled or enabled, otherwise we would be incorrectly setting it or duplicating the metadata, respectively. This should fix PR27643. Differential Revision: https://reviews.llvm.org/D69628
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