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* Implement equal_range for the DWARF v5 accelerator tablePavel Labath2018-02-244-56/+540
| | | | | | | | | | | | | | | | | | | Summary: This patch implements the name lookup functionality of the .debug_names accelerator table and hooks it up to "llvm-dwarfdump -find". To make the interface of the two kinds of accelerator tables more consistent, I've created an abstract "DWARFAcceleratorTable::Entry" class, which provides a consistent interface to access the common functionality of the table entries (such as getting the die offset, die tag, etc.). I've also modified the apple table to vend entries conforming to this interface. Reviewers: JDevlieghere, aprantl, probinson, dblaikie Subscribers: vleschuk, clayborg, echristo, llvm-commits Differential Revision: https://reviews.llvm.org/D43067 llvm-svn: 326003
* Delete dead code in MachVMMemory.cpp, NFCVedant Kumar2018-02-241-36/+0
| | | | | | This addresses a compiler warning. llvm-svn: 326002
* [unittests] Disable lldb-server tests if an external debug server is in useVedant Kumar2018-02-242-3/+9
| | | | | | | | | | | | The lldb-server unit tests don't test the right thing when the debug server in use is copied from somewhere else. This can lead to spurious test failures. Disable these unit tests when an external debug server is in use. Fixes llvm.org/PR36494. llvm-svn: 326001
* [MemorySSA] Remove a redundant dyn_cast.George Burgess IV2018-02-241-3/+2
| | | | | | StartingAccess is a MemoryUseOrDef. No need to check again. llvm-svn: 326000
* [X86] Remove checks for '(scalar_to_vector (i8 (trunc GR32:)))' from scalar ↵Craig Topper2018-02-242-14/+8
| | | | | | | | masked move patterns. This portion can be matched by other patterns. We don't need it to make the larger pattern valid. It's sufficient to have a v1i1 mask input without caring where it came from. llvm-svn: 325999
* Add another test for PR36157.Richard Smith2018-02-241-0/+8
| | | | llvm-svn: 325998
* [ExprConstant] Fix crash when initialize an indirect field with another field.Volodymyr Sapsai2018-02-232-4/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | When indirect field is initialized with another field, you have MemberExpr with CXXThisExpr that corresponds to the field's immediate anonymous parent. But 'this' was referring to the non-anonymous parent. So when we were building LValue Designator, it was incorrect as it had wrong starting point. Usage of such designator would cause unexpected APValue changes and crashes. The fix is in adjusting 'this' for indirect fields from non-anonymous parent to the field's immediate parent. Discovered by OSS-Fuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4985 rdar://problem/36359187 Reviewers: rsmith, efriedma Reviewed By: rsmith Subscribers: cfe-commits, jkorous-apple Differential Revision: https://reviews.llvm.org/D42498 llvm-svn: 325997
* bpf: Hook target feature "alu32" with LLVMYonghong Song2018-02-231-1/+8
| | | | | | | | | | | | | | LLVM has supported a new target feature "alu32" which could be enabled or disabled by "-mattr=[+|-]alu32" when using llc. This patch link Clang with it, so it could be also done by passing related options to Clang, for example: -Xclang -target-feature -Xclang +alu32 Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325996
* [AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC.Stanislav Mekhanoshin2018-02-231-33/+45
| | | | llvm-svn: 325995
* [Sema][ObjC] Process category attributes before checking protocol usesAlex Lorenz2018-02-232-4/+25
| | | | | | | | | This ensures that any availability attributes are attached to the category before the availability for the referenced protocols is checked. rdar://37829755 llvm-svn: 325994
* bpf: New disassembler testcases for 32-bit subregister supportYonghong Song2018-02-233-7/+40
| | | | | | | | | | | | This patch test disassembler output for load/store instructions when -mattr=+alu32 specified for which we want to use "w" register format. Also, this patch extended the existing insn-unit.s and insn-unit-32.s to make sure disassemblers for all other instructions are not affected. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325993
* bpf: New codegen testcases for 32-bit subregister supportYonghong Song2018-02-234-0/+541
| | | | | | | | | | This patch adds some unit tests for 32-bit subregister support. We want to make sure ALU32, subregister load/store and new peephole optimization are truely enabled once -mattr=+alu32 specified. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325992
* bpf: New optimization pass for eliminating unnecessary i32 promotionsYonghong Song2018-02-234-0/+197
| | | | | | | | | | | | | | | | | | This pass performs peephole optimizations to cleanup ugly code sequences at MachineInstruction layer. Currently, the only optimization in this pass is to eliminate type promotion sequences for zero extending 32-bit subregisters to 64-bit registers. If the compiler could prove the zero extended source come from 32-bit subregistere then it is safe to erase those promotion sequece, because the upper half of the underlying 64-bit registers were zeroed implicitly already. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325991
* bpf: New decoder namespace for 32-bit subregister load/storeYonghong Song2018-02-231-2/+43
| | | | | | | | | | | | | | | | | | | | | | | When -mattr=+alu32 passed to the disassembler, use decoder namespace for 32-bit subregister. This is to disassemble load and store instructions in preferred B format as described in previous commit: w = *(u8 *) (r + off) // BPF_LDX | BPF_B w = *(u16 *)(r + off) // BPF_LDX | BPF_H w = *(u32 *)(r + off) // BPF_LDX | BPF_W *(u8 *) (r + off) = w // BPF_STX | BPF_B *(u16 *)(r + off) = w // BPF_STX | BPF_H *(u32 *)(r + off) = w // BPF_STX | BPF_W NOTE: all other instructions should still use the default decoder namespace. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325990
* bpf: Enable 32-bit subregister support for -mattr=+alu32Yonghong Song2018-02-231-0/+2
| | | | | | | | | After all those preparation patches, now we could enable 32-bit subregister support once -mattr=+alu32 specified. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325989
* bpf: Support 32-bit subregister in various InstrInfo hooksYonghong Song2018-02-231-0/+10
| | | | | | | | | This patch support 32-bit subregister in three InstrInfo hooks, i.e. copyPhysReg, loadRegFromStackSlot and storeRegToStackSlot, Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325988
* bpf: New instruction patterns for 32-bit subregister load and storeYonghong Song2018-02-232-10/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The instruction mapping between eBPF/arm64/x86_64 are: eBPF arm64 x86_64 LD1 BPF_LDX | BPF_B ldrb movzbl LD2 BPF_LDX | BPF_H ldrh movzwl LD4 BPF_LDX | BPF_W ldr movl movzbl/movzwl/movl on x86_64 accept 32-bit sub-register, for example %eax, the same for ldrb/ldrh on arm64 which accept 32-bit "w" register. And actually these instructions only accept sub-registers. There is no point to have LD1/2/4 (unsigned) for 64-bit register, because on these arches, upper 32-bits are guaranteed to be zeroed by hardware or VM, so load into the smallest available register class is the best choice for maintaining type information. For eBPF we should adopt the same philosophy, to change current format (A): r = *(u8 *) (r + off) // BPF_LDX | BPF_B r = *(u16 *)(r + off) // BPF_LDX | BPF_H r = *(u32 *)(r + off) // BPF_LDX | BPF_W *(u8 *) (r + off) = r // BPF_STX | BPF_B *(u16 *)(r + off) = r // BPF_STX | BPF_H *(u32 *)(r + off) = r // BPF_STX | BPF_W into B: w = *(u8 *) (r + off) // BPF_LDX | BPF_B w = *(u16 *)(r + off) // BPF_LDX | BPF_H w = *(u32 *)(r + off) // BPF_LDX | BPF_W *(u8 *) (r + off) = w // BPF_STX | BPF_B *(u16 *)(r + off) = w // BPF_STX | BPF_H *(u32 *)(r + off) = w // BPF_STX | BPF_W There is no change on encoding nor how should they be interpreted, everything is as it is, load the specified length, write into low bits of the register then zeroing all remaining high bits. The only change is their associated register class and how compiler view them. Format A still need to be kept, because eBPF LLVM backend doesn't support sub-registers at default, but once 32-bit subregister is enabled, it should use format B. This patch implemented this together with all those necessary extended load and truncated store patterns. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325987
* bpf: Support i32 in getScalarShiftAmountTy methodYonghong Song2018-02-232-0/+7
| | | | | | | | | | getScalarShiftAmount method should be implemented for eBPF backend to make sure shift amount could still get correct type once 32-bit subregisters support are enabled. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325986
* bpf: Support condition comparison on i32Yonghong Song2018-02-233-27/+126
| | | | | | | | | | | | | | | | | | | We need to support condition comparison on i32. All these comparisons are supposed to be combined into BPF_J* instructions which only support i64. For ISD::BR_CC we need to promote it to i64 first, then do custom lowering. For ISD::SET_CC, just expand to SELECT_CC like what's been done for i64. For ISD::SELECT_CC, we also want to do custom lower for i32. However, after 32-bit subregister support enabled, it is possible the comparison operands are i32 while the selected value are i64, or the comparison operands are i64 while the selected value are i32. We need to define extra instruction pattern and support them in custom instruction inserter. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325985
* bpf: Handle i32 for ALU operations without ISA supportYonghong Song2018-02-231-21/+26
| | | | | | | | | | | | There is no eBPF ISA support for BSWAP, ROTR, ROTL, SREM, SDIVREM, MULHU, ADDC, ADDE etc on i32. They could be emulated by other basic BPF_ALU operations, we'd set their lowering action the same as i64. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325984
* bpf: New calling convention for 32-bit subregistersYonghong Song2018-02-233-9/+37
| | | | | | | | | | | This patch add new calling conventions to allow GPR32RegClass as valid register class for arguments and return types. New calling convention will only be choosen when -mattr=+alu32 specified. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325983
* bpf: New target attribute "alu32" for 32-bit subregister supportYonghong Song2018-02-233-0/+9
| | | | | | | | | | | | | | | | | | This new attribute aims to control the enablement of 32-bit subregister support on eBPF backend. Name the interface as "alu32" is because we in particular want to enable the generation of BPF_ALU32 instructions by enable subregister support. This attribute could be used in the following format with llc: llc -mtriple=bpf -mattr=[+|-]alu32 It is disabled at default. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325982
* bpf: Define instruction patterns for extensions and truncations between i32 ↵Yonghong Song2018-02-231-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | to i64 For transformations between i32 and i64, if it is explicit signed extension: - first cast the operand to i64 - then use SLL + SRA to finish the extension. if it is explicit zero extension: - first cast the operand to i64 - then use SLL + SRL to finish the extension. if it is explicit any extension: - just refer to 64-bit register. if it is explicit truncation: - just refer to 32-bit subregister. NOTE: Some of the zero extension sequences might be unnecessary, they will be removed by an peephole pass on MachineInstruction layer. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325981
* bpf: Tighten the immediate predication for 32-bit alu instructionsYonghong Song2018-02-231-2/+4
| | | | | | | | | | | | | | | | | These 32-bit ALU insn patterns which takes immediate as one operand were initially added to enable AsmParser support, and the AsmMatcher uses "ins" and "outs" fields to deduct the operand constraint. However, the instruction selector doesn't work the same as AsmMatcher. The selector will use the "pattern" field for which we are not setting the predication for immediate operands correctly. Without this patch, i32 would eventually means all i32 operands are valid, both imm and gpr, while these patterns should allow imm only. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325980
* bpf: Use markSuperRegs to mark reserved registersYonghong Song2018-02-231-2/+2
| | | | | | | | | markSuperRegs is the canonical helper function used to mark reserved registers. It could mark any overlapping sub-registers automatically. Reviewed-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 325979
* [CFG] Try to narrow down MSVC compiler crash via binary search.Artem Dergachev2018-02-231-11/+17
| | | | | | | | | | Split the presumably offending function in two to see which part of it causes the crash to occur. The crash was introduced in r325966. r325969 did not help. llvm-svn: 325978
* [analyzer] Relax the assert used when traversing the node graph.George Karpenkov2018-02-232-1/+22
| | | | | | | | | | | | | | The assertion gets exposed when changing the exploration order. This is a quick hacky fix, but the intention is that if the nodes do merge, it should not matter which predecessor should be traverse. A proper fix would be not to traverse predecessors at all, as all information relevant for any decision should be avilable locally. rdar://37540480 Differential Revision: https://reviews.llvm.org/D42773 llvm-svn: 325977
* [analyzer] mark returns of functions where the region passed as parameter ↵George Karpenkov2018-02-236-5/+772
| | | | | | | | | | | | | | | | | | was not initialized In the wild, many cases of null pointer dereference, or uninitialized value read occur because the value was meant to be initialized by the inlined function, but did not, most often due to error condition in the inlined function. This change highlights the return branch taken by the inlined function, in order to help user understand the error report and see why the value was uninitialized. rdar://36287652 Differential Revision: https://reviews.llvm.org/D41848 llvm-svn: 325976
* [analyzer] Consider switch- and goto- labels when constructing the set of ↵George Karpenkov2018-02-234-6/+77
| | | | | | | | | | | | executed lines When viewing the report in the collapsed mode the label signifying where did the execution go is often necessary for properly understanding the context. Differential Revision: https://reviews.llvm.org/D43145 llvm-svn: 325975
* Fix a compiler warning in ModuleCacheTest.cpp, NFCVedant Kumar2018-02-231-2/+2
| | | | llvm-svn: 325974
* [DebugInfo] Add remaining files to r325970Scott Linder2018-02-2312-0/+224
| | | | | | Add files which I missed in the original check-in llvm-svn: 325973
* [PowerPC] Disable shrink-wrapping when getting PC address through the LRNemanja Ivanovic2018-02-234-0/+93
| | | | | | | | | | | | | | The instruction sequence used to get the address of the PC into a GPR requires that we clobber the link register. Doing so without having first saved it in the prologue leaves the function unable to return. Currently, this sequence is emitted into the entry block. To ensure the prologue is inserted before this sequence, disable shrink-wrapping. This fixes PR33547. Differential Revision: https://reviews.llvm.org/D43677 llvm-svn: 325972
* [MemorySSA] Fix a cache invalidation bug with removed accessesGeorge Burgess IV2018-02-233-3/+45
| | | | | | | I suspect there's a deeper issue here, but we probably shouldn't be using INVALID_MEMORYSSA_ID as liveOnEntry's ID anyway. llvm-svn: 325971
* [DebugInfo] Support DWARF v5 source code embedding extensionScott Linder2018-02-2351-221/+581
| | | | | | | | | | | | | | | | | | | In DWARF v5 the Line Number Program Header is extensible, allowing values with new content types. In this extension a content type is added, DW_LNCT_LLVM_source, which contains the embedded source code of the file. Add new optional attribute for !DIFile IR metadata called source which contains source text. Use this to output the source to the DWARF line table of code objects. Analogously extend METADATA_FILE in Bitcode and .file directive in ASM to support optional source. Teach llvm-dwarfdump and llvm-objdump about the new values. Update the output format of llvm-dwarfdump to make room for the new attribute on file_names entries, and support embedded sources for the -source option in llvm-objdump. Differential Revision: https://reviews.llvm.org/D42765 llvm-svn: 325970
* [CFG] NFC: Speculative attempt to fix MSVC internal compiler error on buildbot.Artem Dergachev2018-02-231-3/+6
| | | | | | Don't use fancy initialization and member access in a DenseMap. llvm-svn: 325969
* [InstCombine] simplify code for fabs(X) * fabs(X) -> X * X; NFCSanjay Patel2018-02-231-13/+4
| | | | llvm-svn: 325968
* Sink the verification code around the assert where it's handled and wrap in ↵Eric Christopher2018-02-231-25/+14
| | | | | | | | | | NDEBUG. This has the advantage of making release only builds more warning free and there's no need to make this routine a class function if it isn't using class members anyhow. llvm-svn: 325967
* [CFG] [analyzer] NFC: Allow more complicated construction contexts.Artem Dergachev2018-02-232-33/+97
| | | | | | | | | | | | | | ConstructionContexts introduced in D42672 are an additional piece of information included with CFGConstructor elements that help the client of the CFG (such as the Static Analyzer) understand where the newly constructed object is stored. The patch refactors the ConstructionContext class to prepare for including multi-layered contexts that are being constructed gradually, layer-by-layer, as the AST is traversed. Differential Revision: https://reviews.llvm.org/D43428 llvm-svn: 325966
* [InstSimplify] sqrt(X) * sqrt(X) --> XSanjay Patel2018-02-234-15/+21
| | | | | | This was misplaced in InstCombine. We can loosen the FMF as a follow-up step. llvm-svn: 325965
* [Utility] Simplify and generalize the CleanUp helper, NFCVedant Kumar2018-02-237-300/+125
| | | | | | | | | | | | | | | | | | Removing the template arguments and most of the mutating methods from CleanUp makes it easier to understand and reuse. In its present state, CleanUp would be too cumbersome to adapt to cases where multiple objects need to be released. Take for example this change in swift-lldb: https://github.com/apple/swift-lldb/pull/334/files#diff-6f474df750f75c8ba675f2a8408a5629R219 This change is simple to express with the new CleanUp, but not so simple with the old version. Differential Revision: https://reviews.llvm.org/D43662 llvm-svn: 325964
* [ELF] Fix IsPreemptible comment and typo. NFCFangrui Song2018-02-233-4/+4
| | | | llvm-svn: 325963
* Intrinsics calls should avoid the PLT when "RtLibUseGOT" metadata is present.Sriraman Tallam2018-02-235-2/+46
| | | | | | Differential Revision: https://reviews.llvm.org/D42216 llvm-svn: 325962
* Set Module Metadata "RtLibUseGOT" when fno-plt is used.Sriraman Tallam2018-02-232-1/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D42217 llvm-svn: 325961
* [InstCombine] allow fmul-sqrt folds with less than full -ffast-mathSanjay Patel2018-02-234-39/+59
| | | | | | Also, add a Builder method for intrinsics to reduce code duplication for clients. llvm-svn: 325960
* Simplify a DEBUG statement to remove a set but not used variable in release ↵Eric Christopher2018-02-231-7/+4
| | | | | | builds. llvm-svn: 325959
* Fix breakpoint thread name conditionals after breakpoint options refactor.Jim Ingham2018-02-233-39/+42
| | | | | | PR36435 llvm-svn: 325958
* [X86] Add assembler/disassembler support for blendm with zero masking and ↵Craig Topper2018-02-233-0/+192
| | | | | | | | broacast. Fixes PR31617 llvm-svn: 325957
* [Power9] Add missing instructions to the Power 9 schedulerStefan Pintilie2018-02-231-47/+97
| | | | | | | | | | This is the first in a series of patches that will define more instructions using InstRW so that we can move away from ItinRW and ultimately have a complete Power 9 scheduler. Differential Revision: https://reviews.llvm.org/D43635 llvm-svn: 325956
* Remove dead code.Rui Ueyama2018-02-231-2/+0
| | | | llvm-svn: 325955
* [Hexagon] Recognize non-immediate constants in HexagonConstPropagationKrzysztof Parzyszek2018-02-233-6/+36
| | | | llvm-svn: 325954
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