diff options
| author | Yonghong Song <yhs@fb.com> | 2018-02-23 23:49:30 +0000 |
|---|---|---|
| committer | Yonghong Song <yhs@fb.com> | 2018-02-23 23:49:30 +0000 |
| commit | ca31c3bb3ff149850b664838fbbc7d40ce571879 (patch) | |
| tree | 1bb9a05893d677789d2142db855075acf12c57e0 | |
| parent | fcd1e0f62586f371dfd5921be84d5bfd636417fc (diff) | |
| download | bcm5719-llvm-ca31c3bb3ff149850b664838fbbc7d40ce571879.tar.gz bcm5719-llvm-ca31c3bb3ff149850b664838fbbc7d40ce571879.zip | |
bpf: Enable 32-bit subregister support for -mattr=+alu32
After all those preparation patches, now we could enable 32-bit subregister
support once -mattr=+alu32 specified.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 325989
| -rw-r--r-- | llvm/lib/Target/BPF/BPFISelLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index 0d604e099c3..4ad99e798fb 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -57,6 +57,8 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, // Set up the register classes. addRegisterClass(MVT::i64, &BPF::GPRRegClass); + if (STI.getHasAlu32()) + addRegisterClass(MVT::i32, &BPF::GPR32RegClass); // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); |
