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* Fix crash when linking metadata with ODR type uniquingTeresa Johnson2018-01-093-1/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: With DebugTypeODRUniquing enabled, during IR linking debug metadata in the destination module may be reached from the source module. This means that ConstantAsMetadata nodes (e.g. on DITemplateValueParameter) may contain a value the destination module. When trying to map such metadata nodes, we will attempt to map a GV already in the dest module. linkGlobalValueProto will end up with a source GV that is the same as the dest GV as well as the new GV. Trying to access the TypeMap for the source GV type, which is actually a dest GV type, hits an assertion since it appears that we have mapped into the source module (because the type is the value not a key into the map). Detect that we don't need to access the TypeMap in this case, since there is no need to create a bitcast from the new GV to the source GV type as they GV are the same. Fixes PR35722. Reviewers: mehdi_amini, pcc Subscribers: probinson, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D41624 llvm-svn: 322103
* [lit] Implement "-r" option for builtin "diff" command + a test using that.Max Moroz2018-01-0912-15/+245
| | | | | | | | | | | | | | | | Summary: That would allow to recursively compare directories in tests using "diff -r" on Windows in a similar way as it can be done on Linux or Mac. Reviewers: zturner, morehouse, vsk Reviewed By: zturner Subscribers: kcc, llvm-commits Differential Revision: https://reviews.llvm.org/D41776 llvm-svn: 322102
* [X86] Add a DAG combine to combine (sext (setcc)) with VLXCraig Topper2018-01-0911-264/+149
| | | | | | | | | | | | Normally target independent DAG combine would do this combine based on getSetCCResultType, but with VLX getSetCCResultType returns a vXi1 type preventing the DAG combining from kicking in. But doing this combine can allow us to remove the explicit sign extend that would otherwise be emitted. This patch adds a target specific DAG combine to combine the sext+setcc when the result type is the same size as the input to the setcc. I've restricted this to FP compares and things that can be represented with PCMPEQ and PCMPGT since we don't have full integer compare support on the older ISAs. Differential Revision: https://reviews.llvm.org/D41850 llvm-svn: 322101
* [lli] Make lli support -mcpu=native for CPU autodetectionCraig Topper2018-01-092-2/+22
| | | | | | | | | | | | llc, opt, and clang can all autodetect the CPU and supported features. lli cannot as far as I could tell. This patch uses the getCPUStr() and introduces a new getCPUFeatureList() and uses those in lli in place of MCPU and MAttrs. Ideally, we would merge getCPUFeatureList and getCPUFeatureStr, but opt and llc need a string and lli wanted a list. Maybe we should just return the SubtargetFeature object and let the caller decide what it needs? Differential Revision: https://reviews.llvm.org/D41833 llvm-svn: 322100
* Test commitMatthew Voss2018-01-091-1/+1
| | | | | | This is a commit to test commit access. llvm-svn: 322099
* [TargetParser] Add missing armv8l ARMv8 variant.Florian Hahn2018-01-092-18/+19
| | | | | | | | | | | | | | | | | | This change adds the missing armv8l variant as an alias of armv8 architecture. The issue was observed with several regressions in validation on armv8l hardware (for instance ExecutionEngine/frem.ll failed due to lack of neon fpu). Tested with regression testsuite passed without regression on ARM and x86_64. Patch by Yvan Roux. Reviewers: rengolin, rogfer01, olista01, fhahn Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D41859 llvm-svn: 322098
* [clangd] Add more symbol information for code completion.Eric Liu2018-01-0911-23/+220
| | | | | | | | | | | | Reviewers: hokein, sammccall Reviewed By: sammccall Subscribers: klimek, ilya-biryukov, cfe-commits Differential Revision: https://reviews.llvm.org/D41345 llvm-svn: 322097
* [CodeGen] Don't print "pred:" and "opt:" in -debug outputFrancis Visoiu Mistrih2018-01-0912-47/+41
| | | | | | | | | | In -debug output we print "pred:" whenever a MachineOperand is a predicate operand in the instruction descriptor, and "opt:" whenever a MachineOperand is an optional def in the instruction descriptor. Differential Revision: https://reviews.llvm.org/D41870 llvm-svn: 322096
* [Support] Use realpath(3) instead of trying to open a file.Davide Italiano2018-01-092-6/+25
| | | | | | | | | If we don't have read permissions on the directory the call would fail. <rdar://problem/35871293> llvm-svn: 322095
* [Support] Add WritableMemoryBuffer::getNewMemBufferPavel Labath2018-01-094-14/+23
| | | | | | | | | | | | | | | | | | Summary: The idea is that it would replace (non-Writable)MemoryBuffer::getNewMemBuffer, which is quite useless unless you const_cast its contents to write to it (which all (both) callers of this function were doing). This patch also fixes one of the usages in COFFWriter. After fixing the other usage in clang, I plan to delete the old function. Reviewers: dblaikie, Bigcheese Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41540 llvm-svn: 322094
* [libunwind][MIPS]: Rename Registers_mips_n64 to Registers_mips_newabi.John Baldwin2018-01-095-40/+40
| | | | | | | | | | | This is in preparation for adding support for N32 unwinding which reuses the newabi register class. Reviewed By: compnerd Differential Revision: https://reviews.llvm.org/D41842 llvm-svn: 322093
* Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructionsSander de Smalen2018-01-098-4/+300
| | | | | | | | | Fixed issue that was found on sanitizer-x86_64-linux-fast. I changed the result type of 'Parser.getTok().getString().lower()' in AArch64AsmParser::tryParseSVEPredicateVector() from 'StringRef' to 'auto', since StringRef::lower() returns a std::string. llvm-svn: 322092
* [ASTImporter] Support importing CXXUnresolvedConstructExpr and ↵Aleksei Sidorin2018-01-092-0/+96
| | | | | | | | | | | | | UnresolvedLookupExpr * Note: This solution is based on https://github.com/haoNoQ/clang/blob/summary-ipa-draft/lib/AST/ASTImporter.cpp#L7605. Patch by Peter Szecsi! Differential Revision: https://reviews.llvm.org/D38694 llvm-svn: 322091
* X86 Tests: Update more isel tests with FastVariableShuffle featureZvi Rackover2018-01-0929-1598/+2675
| | | | | | | | | | | | | | | | | Summary: Added the FastVariableShuffle feature to cases that resembled processors for which this fearure is on. For AVX2 there are processors with and w/o this fearue enable. For AVX512 only KNL does enable this feature so cases which only have +avx512f were left without the FastVariableShuffle enabled. Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41851 llvm-svn: 322090
* X86 Tests: Add common check prefix to test-case. NFC.Zvi Rackover2018-01-091-31/+1
| | | | | | As suggested in D41851 llvm-svn: 322089
* [CodeGen] Print frame-setup/destroy flags in -debug output like we do in MIRFrancis Visoiu Mistrih2018-01-092-16/+6
| | | | | | | | | | | | | | | Currently the MachineInstr::print function prints the frame-setup/frame-destroy differently than it does in MIR. Instead of: %x21 = LDR %sp, -16; flags: FrameDestroy print: %x21 = frame-destroy LDR %sp, -16 llvm-svn: 322088
* [SelectionDAG] lower math intrinsics to finite version of libcalls when ↵Sanjay Patel2018-01-096-34/+485
| | | | | | | | | | | | | | | | | | | | | | possible (PR35672) Ingredients in this patch: 1. Add HANDLE_LIBCALL defs for finite mathlib functions that correspond to LLVM intrinsics. 2. Plumbing to send TargetLibraryInfo down to SelectionDAGLegalize. 3. Relaxed math and library checking in SelectionDAGLegalize::ConvertNodeToLibcall() to choose finite libcalls. There was a bug about determining the availability of the finite calls that should be fixed with: rL322010 Not in this patch: This doesn't resolve the question/bug of clang creating the intrinsic IR in the first place. There's likely follow-up work needed to support the long double variants better. There's room for improvement to reduce the code duplication. Create finite calls that don't originate from a corresponding intrinsic or DAG node? Differential Revision: https://reviews.llvm.org/D41338 llvm-svn: 322087
* [CodeGen] Don't print register classes in -debug outputFrancis Visoiu Mistrih2018-01-099-74/+37
| | | | | | | | | | Since register classes and banks are already printed with the register definition, don't print it at the end of every instruction anymore. This follows MIR in this regard and is another step to the unification of the two formats. llvm-svn: 322086
* [DAG] Elide overlapping storesNirav Dave2018-01-092-24/+22
| | | | | | | | | | | | | | | | Relanding after fixing handling of pre-indexed memory operations in BaseIndexOffset analysis (r322003). Extend overlapping store elision to handle overwrites of stores by larger stores. Reviewers: craig.topper, rnk, t.p.northover Subscribers: javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40969 llvm-svn: 322085
* [clangd] Use ToolExecutor to write the global-symbol-builder tool.Eric Liu2018-01-094-52/+64
| | | | | | | | | | | | | | | Summary: This enables more execution modes like standalone and Mapreduce-style execution. See also D41729 Reviewers: hokein, sammccall Subscribers: klimek, ilya-biryukov, cfe-commits Differential Revision: https://reviews.llvm.org/D41730 llvm-svn: 322084
* [EarlyCSE] Salvage debug info during DCEPetar Jovanovic2018-01-092-0/+65
| | | | | | | | | | | EarlyCSE did not try to salvage debug info during erasing of instructions. This change fixes it. Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D41496 llvm-svn: 322083
* Explicitly specify output file.Alexander Kornienko2018-01-091-2/+2
| | | | | | Otherwise the test fails when LLVM sources are on a read-only partition. llvm-svn: 322082
* [test] Fix tests to use more portable LLVM_ENABLE_ZLIBMichal Gorny2018-01-092-1/+5
| | | | | | | | | | | | | The HAVE_LIBZ variable is not exported by LLVM, and therefore is not available in stand-alone builds of other tools. Use LLVM_ENABLE_ZLIB which is the name under which the effective value is exported. Additional, use llvm_canonicalize_cmake_booleans() to make sure that a correct (Python-safe) boolean value is passed down to lit. Differential Revision: https://reviews.llvm.org/D41725 llvm-svn: 322081
* [clangd] Fix a bug in asynchronous code completionIlya Biryukov2018-01-091-2/+9
| | | | | | | | | A StringRef that goes out of scope was copied and used in a handler running on a separate thread. We didn't catch it because clangd does not use the async completion API yet. llvm-svn: 322080
* [ASTImporter] Fix missing SourceLoc import for ObjCMethodDecl selectorsAleksei Sidorin2018-01-092-2/+8
| | | | | | | | Patch by Nico Rieck, test case by Sean Callanan! Differential Revision: https://reviews.llvm.org/D6550 llvm-svn: 322079
* [InstCombine] Check for out of range ashr values using APInt before calling ↵Simon Pilgrim2018-01-092-3/+28
| | | | | | | | getZExtValue Reduced from oss-fuzz #5032 test case llvm-svn: 322078
* Reverted r322073 because of AddressSanitizer failure onSander de Smalen2018-01-097-299/+3
| | | | | | sanitizer-x86_64-linux-fast builder. llvm-svn: 322077
* [X86][AVX] Add v2i64/v2f64 load testsSimon Pilgrim2018-01-091-0/+29
| | | | | | Ensure these use insertions, not masked load ops llvm-svn: 322076
* TestConflictingSymbols: simplify test by using run_break_set_by_source_regexpPavel Labath2018-01-091-14/+8
| | | | | | follow-up to r321271 based on post-commit feedback by Jim Ingham. llvm-svn: 322075
* Track in the AST whether the operand to a UnaryOperator can overflow and ↵Aaron Ballman2018-01-0918-180/+245
| | | | | | then use that logic when evaluating constant expressions and emitting codegen. llvm-svn: 322074
* [AArch64][SVE] Asm: Add predicated ADD/SUB instructionsSander de Smalen2018-01-097-3/+299
| | | | | | | | | | | | | | | | | Summary: Add the predicated ADD/SUB instructions and corresponding tests. Patch [3/3] in a series to add predicated ADD/SUB instructions for SVE. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41443 llvm-svn: 322073
* [InstCombine] Add pow2 mul -> shl tests for vectors with uniform/non-uniform ↵Simon Pilgrim2018-01-092-13/+57
| | | | | | constants llvm-svn: 322072
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-097-3/+17
| | | | | | | | | We are printing / parsing the `frame-setup` MachineInstr flag but not the `frame-destroy` one. Differential Revision: https://reviews.llvm.org/D41509 llvm-svn: 322071
* [AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate ↵Sander de Smalen2018-01-092-0/+32
| | | | | | | | | | | | | | | | | | | vector operands Summary: Parsing of the '/m' (merging) or '/z' (zeroing) suffix of a predicate operand. Patch [2/3] in a series to add predicated ADD/SUB instructions for SVE. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, MatzeB, t.p.northover Reviewed By: fhahn Subscribers: t.p.northover, MatzeB, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41442 llvm-svn: 322070
* [Nios2] Arithmetic instructions for R1 and R2 ISA.Nikolai Bozhenov2018-01-098-11/+210
| | | | | | | | | | | | | | Summary: This commit enables some of the arithmetic instructions for Nios2 ISA (for both R1 and R2 revisions), implements facilities required to emit those instructions and provides LIT tests for added instructions. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D41236 Author: belickim <mateusz.belicki@intel.com> llvm-svn: 322069
* Fix type mismatch in omp_control_tool() implementation that makes it run ↵Paul Osmialowski2018-01-091-1/+1
| | | | | | | | incorrectly on 32-bit machines. Differential Revision: https://reviews.llvm.org/D41854 llvm-svn: 322068
* [clangd] Catch more symbols in SymbolCollector.Haojian Wu2018-01-092-4/+49
| | | | | | | | | | | | | | | | | | Summary: We currently only collect external-linkage symbols in the collector, which results in missing some typical symbols (like no-linkage type alias symbols). This patch relaxes the constraint a bit to allow collecting more symbols. Reviewers: ilya-biryukov Reviewed By: ilya-biryukov Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D41759 llvm-svn: 322067
* [ELF] Add a comment for ARMExidxSentinelSection::Highest; Use "= nullptr" ↵Igor Kudrin2018-01-091-1/+4
| | | | | | | | instead of "= 0". NFC. Differential Revision: https://reviews.llvm.org/D41234 llvm-svn: 322066
* Avoid assumption that lit tests are writable (in a couple more places). NFCSam McCall2018-01-092-4/+4
| | | | llvm-svn: 322065
* ananas: Add shared library supportEd Schouten2018-01-092-5/+33
| | | | | | | | | | | | | The Ananas Operating System (https://github.com/zhmu/ananas) has shared library support as of commit 57739c0b6ece56dd4872aedf30264ed4b9412c77. This change adds the necessary settings to clang so that shared executables and libraries can be build correctly. Submitted by: Rink Springer Differential Revision: https://reviews.llvm.org/D41500 llvm-svn: 322064
* Added Control Flow Protection FlagOren Ben Simhon2018-01-0912-2/+105
| | | | | | | | | | Cf-protection is a target independent flag that instructs the back-end to instrument control flow mechanisms like: Branch, Return, etc. For example in X86 this flag will be used to instrument Indirect Branch Tracking instructions. Differential Revision: https://reviews.llvm.org/D40478 Change-Id: I5126e766c0e6b84118cae0ee8a20fe78cc373dea llvm-svn: 322063
* Instrument Control Flow For Indirect Branch TrackingOren Ben Simhon2018-01-098-2/+386
| | | | | | | | | | | | | CET (Control-Flow Enforcement Technology) introduces a new mechanism called IBT (Indirect Branch Tracking). According to IBT, each Indirect branch should land on dedicated ENDBR instruction (End Branch). The new pass adds ENDBR instructions for every indirect jmp/call (including jumps using jump tables / switches). For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40482 Change-Id: Icb754489faf483a95248f96982a4e8b1009eb709 llvm-svn: 322062
* [cmake] Use symlinks for Windows-hosted toolchains built on UnixShoaib Meenai2018-01-092-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When cross-compiling for Windows on Unix, the built toolchain will need to be transferred to Windows to actually run. My opinion is that the Unix build should use symlinks, and the transfer to Windows should take care of making those symlinks usable. E.g., I envision tarballs to be a common form of transfer from Unix to Windows, in which case the tarball can be created using --dereference to follow the symlinks. The motivation here is that, when cross-compiling for Windows on Unix, the installation will *already* create symlinks. The reason is that the installation script will be invoked without knowing the host system, so the `if(UNIX)` check in the installation symlink creation script will reflect the build system rather than the host system. We could either make the build and install trees both contain copies or both contain symlinks, and using symlinks is a significant space saving without (in my opinion) having any detrimental effect on the usage of the cross- compiled toolchain on Windows. A secondary motivation is that Windows 10 version 1703 and later finally lift the administrator rights requirement for creating symbolic links (if the system is in Developer Mode), which makes symlinks a lot more practical even on Windows. Of course Unix and Windows symlinks aren't interoperable, but symlinks for Windows toolchains is a reasonable future direction to be going in anyway. Differential Revision: https://reviews.llvm.org/D41314 llvm-svn: 322061
* [X86] Allow more cmpps/pd immediate encodings to be commuted during isel.Craig Topper2018-01-092-34/+18
| | | | | | The code that checks the immediate wasn't masking to the lower 3-bits like the code in X86InstrInfo.cpp that's used by the peephole pass does. llvm-svn: 322060
* [SCEV] Do not cache S -> V if S is not equivalent of VSerguei Katkov2018-01-093-3/+124
| | | | | | | | | | | | | | | | SCEV tracks the correspondence of created SCEV to original instruction. However during creation of SCEV it is possible that nuw/nsw/exact flags are lost. As a result during expansion of the SCEV the instruction with nuw/nsw/exact will be used where it was expected and we produce poison incorreclty. Reviewers: sanjoy, mkazantsev, sebpop, jbhateja Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41578 llvm-svn: 322058
* [ELF] Explicit template instantiations for addFileEaswaran Raman2018-01-091-0/+5
| | | | | | | | | | | | | | | Summary: All other templated methods have explicit instantiations but this one is missing. Discovered while building with a clang with inliner modifications. Reviewers: espindola Subscribers: emaste, llvm-commits, davidxl Differential Revision: https://reviews.llvm.org/D41847 llvm-svn: 322057
* [CGP] Fix Complex addressing mode for offsetSerguei Katkov2018-01-092-1/+25
| | | | | | | | | | | | | | If the offset is differ in two addressing mode we can continue only if ScaleReg is not set due to we will use it as merge of different offsets. It should fix PR35799 and PR35805. Reviewers: john.brawn, reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41227 llvm-svn: 322056
* [PowerPC] Can not assume an intrinsic argument is a simple type.Sean Fertile2018-01-092-6/+67
| | | | | | | | | | | | | The CTRLoop pass performs checks on the argument of certain libcalls/intrinsics, and assumes the arguments must be of a simple type. This isn't always the case though. For example if we unroll and vectorize a loop we may end up with vectors larger then the largest legal type, along with intrinsics that operate on those wider types. This happened in the ffmpeg build, where we unrolled a loop and ended up with a sqrt intrinsic that operated on V16f64, triggering an assertion. Differential Revision: https://reviews.llvm.org/D41758 llvm-svn: 322055
* Cut and paste error - I wasn't actually running both tests...Jim Ingham2018-01-091-1/+1
| | | | llvm-svn: 322054
* Remove unused function HvxSelector::zerous.Eric Christopher2018-01-091-20/+0
| | | | llvm-svn: 322053
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