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* Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski2013-03-207-16/+120
| | | | | | | | A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. llvm-svn: 177465
* Fix bug in test; found by AddressSanitizerMarshall Clow2013-03-201-1/+1
| | | | llvm-svn: 177464
* Fix pr13145 - Naming a function like a register name confuses the asm parser.Chad Rosier2013-03-192-14/+25
| | | | | | | Patch by Stepan Dyatkovskiy <stpworld@narod.ru> rdar://13457826 llvm-svn: 177463
* Move the DIFile operand to DITypes from the 4th operand to the 2nd.David Blaikie2013-03-1955-430/+402
| | | | | | | | This is another step along the way to making all DIScopes have a common prefix which can be added to in a general manner to support using directives (DW_TAG_imported_module). llvm-svn: 177462
* Annotate various null idioms with SchedRW lists.Jakob Stoklund Olesen2013-03-191-4/+4
| | | | llvm-svn: 177461
* Annotate SSE float conversions with SchedRW lists.Jakob Stoklund Olesen2013-03-191-60/+81
| | | | llvm-svn: 177460
* Annotate X86InstrCMovSetCC.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-4/+5
| | | | llvm-svn: 177459
* Formatting fixups.Eric Christopher2013-03-191-14/+14
| | | | llvm-svn: 177458
* Simplify/generalize some debug info test casesDavid Blaikie2013-03-1919-80/+78
| | | | | | | | | Mostly, try to depend on the annotation comments more so these tests are more legible, brief, and agnostic to schema changes in the future (sure, they're not agnostic to changes to the comment annotations but since they're easier to read they should be easier to update if that happens). llvm-svn: 177457
* Updated the IRExecutionUnit to keep local copiesSean Callanan2013-03-192-31/+38
| | | | | | | | | | | | | | | | of the data it writes down into the process even if the process doesn't exist. This will allow the IR interpreter to access static data allocated on the expression's behalf. Also cleaned up object ownership in the IRExecutionUnit so that allocations are created into the allocations vector. This avoids needless data copies. <rdar://problem/13424594> llvm-svn: 177456
* [analyzer] Add an integer version of the Circle tests in uninit-vals.m.Jordan Rose2013-03-191-4/+49
| | | | | | | | | A floating-point version is nice for testing unknown values, but it's good to be able to check all parts of the structure as well. Test change only, no functionality change. llvm-svn: 177455
* The formatters for std::shared_ptr, std::weak_ptr, std::list, std::vector ↵Enrico Granata2013-03-1912-837/+1961
| | | | | | | | and std::map as provided by libc++ are now written in C++ instead of Python std::deque is still in Python but is much less commonly used llvm-svn: 177454
* [analyzer] Do not believe lazy binding when symbolic region types do not matchAnna Zaks2013-03-193-11/+46
| | | | | | | | | | | This fixes a crash when analyzing LLVM that was exposed by r177220 (modeling of trivial copy/move assignment operators). When we look up a lazy binding for “Builder”, we see the direct binding of Loc at offset 0. Previously, we believed the binding, which led to a crash. Now, we do not believe it as the types do not match. llvm-svn: 177453
* Marshall Clow found this memory problem in strstream using ↵Howard Hinnant2013-03-191-0/+2
| | | | | | -fsanitize=address on the test suite. llvm-svn: 177452
* Dead code.Chad Rosier2013-03-191-2/+0
| | | | llvm-svn: 177451
* Dead code.Chad Rosier2013-03-191-6/+0
| | | | llvm-svn: 177450
* [analyzer] Add a test case for diagnostic suppression on a graph with cycles.Jordan Rose2013-03-191-0/+19
| | | | | | (see previous commit) llvm-svn: 177449
* Revert "[analyzer] Do part of the work to find shortest bug paths up front."Jordan Rose2013-03-191-115/+42
| | | | | | | | | | | | | The whole reason we were doing a BFS in the first place is because an ExplodedGraph can have cycles. Unfortunately, my removeErrorNode "update" doesn't work at all if there are cycles. I'd still like to be able to avoid doing the BFS every time, but I'll come back to it later. This reverts r177353 / 481fa5071c203bc8ba4f88d929780f8d0f8837ba. llvm-svn: 177448
* Mark TestChangeValueAPI.py as expected fail with gcc as it still reproduces.Matt Kopec2013-03-191-0/+1
| | | | llvm-svn: 177447
* [ms-inline asm] Move the immediate asm rewrite into the target specificChad Rosier2013-03-192-15/+5
| | | | | | | logic as a QOI cleanup. No functional change. Tests already in place. rdar://13456414 llvm-svn: 177446
* Update global merge pass according to Duncan's advices:Quentin Colombet2013-03-191-8/+7
| | | | | | | | - Remove useless includes - Change misleading comments - Move code into doFinalization llvm-svn: 177445
* ScopDetect: Remove some redundant semicolonsTobias Grosser2013-03-191-3/+3
| | | | llvm-svn: 177444
* This is an optimization which produces improved launching time. There ↵Howard Hinnant2013-03-192-20/+22
| | | | | | should be no functionality change. Clients should see no ABI differences. llvm-svn: 177443
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-192-8/+13
| | | | | | | Add a new WriteZero SchedWrite type for the common dependency-breaking instructions that clear a register. llvm-svn: 177442
* Test case for r177439 and r177440.Chad Rosier2013-03-191-0/+13
| | | | llvm-svn: 177441
* [ms-inline asm] Remove the brackets from X86Operand in the IR. These will beChad Rosier2013-03-191-8/+19
| | | | | | | | | | | | | | | | | | | | added back in by X86AsmPrinter::printIntelMemReference() during codegen. Previously, this following example void t() { int i; __asm mov eax, [i] } would generate the below assembly mov eax, dword ptr [[eax]] which resulted in a fatal error when compiling. Test case coming on the clang side. rdar://13444264 llvm-svn: 177440
* [ms-inline asm] Create a helper function, CreateMemForInlineAsm, that createsChad Rosier2013-03-191-36/+49
| | | | | | | | | | an X86Operand, but also performs a Sema lookup and adds the sizing directive when appropriate. Use this when parsing a bracketed statement. This is necessary to get the instruction matching correct as well. Test case coming on clang side. rdar://13455408 llvm-svn: 177439
* IndependentBlocks: Add a couple of test cases.Tobias Grosser2013-03-193-0/+160
| | | | llvm-svn: 177438
* Register the GCOV writeout functions so that they're emitted serially.Bill Wendling2013-03-191-10/+31
| | | | | | | | | We don't want to write out >1000 files at the same time. That could make things prohibitively expensive. Instead, register the "writeout" function so that it's emitted serially. <rdar://problem/12439551> llvm-svn: 177437
* Add a way to register and execute "writeout" functions.Bill Wendling2013-03-191-0/+45
| | | | | | | | | | It may be prohibitively expensive to write out >1000 files at the same time. So we would rather emit them serially. These functions allow the GCOV implementation to register the functions that writeout the GCOV information per compile unit. At exit, they are written. <rdar://problem/12439551> llvm-svn: 177436
* Objective-C [qoi]: Provide improved parse diagnostics whenFariborz Jahanian2013-03-193-0/+12
| | | | | | | | | closing rbrace is missing in an ObjC class declaration. Can do beter than this, but it involves addition of overhead which will be present in correct code. // rdar://6854840 llvm-svn: 177435
* Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll testHal Finkel2013-03-191-0/+2
| | | | llvm-svn: 177434
* ScopDetection: Add a couple of test casesTobias Grosser2013-03-194-0/+162
| | | | llvm-svn: 177433
* IndVarSimplify: do not recompute an IV value outside of the loop if :Arnaud A. de Grandmaison2013-03-192-0/+108
| | | | | | | - it is trivially known to be used inside the loop in a way that can not be optimized away - there is no use outside of the loop which can take advantage of the computation hoisting llvm-svn: 177432
* Add missing mayLoad flag to LHAUX8 and LWAUX.Ulrich Weigand2013-03-191-1/+2
| | | | | | | | | All pre-increment load patterns need to set the mayLoad flag (since they don't provide a DAG pattern). This was missing for LHAUX8 and LWAUX, which is added by this patch. llvm-svn: 177431
* Rewrite LHAU8 pattern to use standard memory operand.Ulrich Weigand2013-03-191-4/+4
| | | | | | | | | | | | As opposed to to pre-increment store patterns, the pre-increment load patterns were already using standard memory operands, with the sole exception of LHAU8. As there's no real reason why LHAU8 should be different here, this patch simply rewrites the pattern to also use a memri operand, just like all the other patterns. llvm-svn: 177430
* Rewrite pre-increment store patterns to use standard memory operands.Ulrich Weigand2013-03-193-151/+291
| | | | | | | | | | | | | | | | | | | | | | Currently, pre-increment store patterns are written to use two separate operands to represent address base and displacement: stwu $rS, $ptroff($ptrreg) This causes problems when implementing the assembler parser, so this commit changes the patterns to use standard (complex) memory operands like in all other memory access instruction patterns: stwu $rS, $dst To still match those instructions against the appropriate pre_store SelectionDAG nodes, the patch uses the new feature that allows a Pat to match multiple DAG operands against a single (complex) instruction operand. Approved by Hal Finkel. llvm-svn: 177429
* Extend TableGen instruction selection matcher to improve handlingUlrich Weigand2013-03-193-11/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. llvm-svn: 177428
* Fix sub-operand size mismatch in tocentry operands.Ulrich Weigand2013-03-191-1/+1
| | | | | | | | | | | The tocentry operand class refers to 64-bit values (it is only used in 64-bit, where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit type. This causes a mismatch to be detected at compile-time with the TableGen patch I'll check in shortly. To fix this, this commit changes the suboperand to a 64-bit type as well. llvm-svn: 177427
* Remove an invalid and unnecessary Pat pattern from the X86 backend:Ulrich Weigand2013-03-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), (MOV64rm tglobaltlsaddr :$dst)>; This pattern is invalid because the MOV64rm instruction expects a source operand of type "i64mem", which is a subclass of X86MemOperand and thus actually consists of five MI operands, but the Pat provides only a single MI operand ("tglobaltlsaddr" matches an SDnode of type ISD::TargetGlobalTLSAddress and provides a single output). Thus, if the pattern were ever matched, subsequent uses of the MOV64rm instruction pattern would access uninitialized memory. In addition, with the TableGen patch I'm about to check in, this would actually be reported as a build-time error. Fortunately, the pattern does in fact never match, for at least two independent reasons. First, the code generator actually never generates a pattern of the form (load (X86Wrapper (tglobaltlsaddr))). For most combinations of TLS and code models, (tglobaltlsaddr) represents just an offset that needs to be added to some base register, so it is never directly dereferenced. The only exception is the initial-exec model, where (tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot, which *is* in fact directly dereferenced: but in that case, the X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match. Second, even if some patterns along those lines *were* ever generated, we should not need an extra Pat pattern to match it. Instead, the original MOV64rm instruction pattern ought to match directly, since it uses an "addr" operand, which is implemented via the SelectAddr C++ routine; this routine is supposed to accept the full range of input DAGs that may be implemented by a single mov instruction, including those cases involving ISD::TargetGlobalTLSAddress (and actually does so e.g. in the initial-exec case as above). To avoid build breaks (due to the above-mentioned error) after the TableGen patch is checked in, I'm removing this Pat here. llvm-svn: 177426
* Update Sketch test case to capture this and use accessors for debugger, ↵Greg Clayton2013-03-192-36/+64
| | | | | | target, process and thread. llvm-svn: 177425
* Fix "control reaches end of non-void function" compiling lld on gcc.Andy Gibbs2013-03-191-1/+2
| | | | llvm-svn: 177424
* Prepare to make r0 an allocatable register on PPCHal Finkel2013-03-197-112/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the PPC r0 register is unconditionally reserved. There are two reasons for this: 1. r0 is treated specially (as the constant 0) by certain instructions, and so cannot be used with those instructions as a regular register. 2. r0 is used as a temporary register in the CR-register spilling process (where, under some circumstances, we require two GPRs). This change addresses the first reason by introducing a restricted register class (without r0) for use by those instructions that treat r0 specially. These register classes have a new pseudo-register, ZERO, which represents the r0-as-0 use. This has the side benefit of making the existing target code simpler (and easier to understand), and will make it clear to the register allocator that uses of r0 as 0 don't conflict will real uses of the r0 register. Once the CR spilling code is improved, we'll be able to allocate r0. Adding these extra register classes, for some reason unclear to me, causes requests to the target to copy 32-bit registers to 64-bit registers. The resulting code seems correct (and causes no test-suite failures), and the new test case covers this new kind of asymmetric copy. As r0 is still reserved, no functionality change intended. llvm-svn: 177423
* Don't replace macro usage if macro body has NULLEdwin Vane2013-03-193-31/+120
| | | | | | | | | | | | | | | | | | | In case of macro body expansion, check to see if the macro is named NULL and don't replace inside the macro body. This fixes the case when NULL appears inside the macro body and the transform replaces the usage of the macro with nullptr. This is an easy fix for the problem for now and we should analyze the macro body to see if it expands to only NullToPointer in the future for a more robust solution that takes care of user defined macros that behaves like NULL. Other changes: - Moved complex macro tests to macros.cpp - Added new test cases. - Added checks to make sure that the macro bodies are not modified by the tool. Fixes: PR15396 Author: Tareq A Siraj <tareq.a.siraj@intel.com> llvm-svn: 177422
* Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.Nadav Rotem2013-03-194-6/+42
| | | | | | Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com> llvm-svn: 177421
* Fix indentation for case: // comment.Daniel Jasper2013-03-192-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | Before: switch (x) { case 1: // Do amazing stuff { g(); f(); } } After: switch (x) { case 1: // Do amazing stuff { g(); f(); } } llvm-svn: 177420
* Relax test to allow for attributes on other architectures. Caught by ↵Adrian Prantl2013-03-191-2/+2
| | | | | | powerpc64-unknown-linux-gnu buildbot. llvm-svn: 177419
* Annotate X86InstrExtension.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-26/+39
| | | | llvm-svn: 177418
* Annotate a lot of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-191-26/+60
| | | | llvm-svn: 177417
* Fixed incorrect python that was trying to validate that we got a valid ↵Greg Clayton2013-03-1915-26/+26
| | | | | | | | lldb.SBThread object by checking to see if it is equal to "None". This test is incorrect as functions that return lldb.SBThread objects never return None, they just return lldb.SBThread objects that contain invalid opaque classes. llvm-svn: 177416
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