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* [APInt] Remove unnecessary early out from getLowBitsSet. The same case is ↵Craig Topper2017-02-262-2/+10
| | | | | | handled equally well by the next check. llvm-svn: 296299
* Update comments. NFCIXin Tong2017-02-261-2/+2
| | | | llvm-svn: 296298
* Fix typo.Rui Ueyama2017-02-261-1/+1
| | | | | | Pointed out by Piotr Padlewski. llvm-svn: 296297
* [X86] DAZ Macros RelocationOren Ben Simhon2017-02-262-8/+8
| | | | | | | | | The DAZ feature introduces the denormal zero support for x86. Currently the definitions are located under SSE3 header, however there are some SSE2 targets that support the feature as well. Differential Revision: https://reviews.llvm.org/D30194 llvm-svn: 296296
* Revert "[CGP] Split some critical edges coming out of indirect branches"Daniel Jasper2017-02-265-435/+13
| | | | | | | This reverts commit r296149 as it leads to crashes when compiling for PPC. llvm-svn: 296295
* [LoopDeletion] Modernize and simplify a bit. NFCI.Davide Italiano2017-02-261-8/+3
| | | | llvm-svn: 296294
* [X86] Fix execution domain for cmpss/sd instructions.Craig Topper2017-02-265-160/+168
| | | | llvm-svn: 296293
* [AVX-512] Fix execution domain for scalar commutable min/max instructions.Craig Topper2017-02-261-1/+1
| | | | llvm-svn: 296292
* [AVX-512] Fix execution domain for vmovhpd/lpd/hps/lps.Craig Topper2017-02-262-1/+2
| | | | llvm-svn: 296291
* [AVX-512] Fix the execution domain for AVX-512 integer broadcasts.Craig Topper2017-02-263-5/+6
| | | | llvm-svn: 296290
* [AVX-512] Disable the redundant patterns in the VPBROADCASTBr_Alt and ↵Craig Topper2017-02-261-14/+16
| | | | | | VPBROADCASTWr_Alt instructions. NFC llvm-svn: 296289
* [AVX-512] Fix execution domain for VPMADD52 instructions.Craig Topper2017-02-263-24/+26
| | | | llvm-svn: 296288
* [AVX-512] Use update_llc_test_checks.py to regenerate a test.Craig Topper2017-02-261-44/+53
| | | | llvm-svn: 296287
* [AVX-512] Fix the execution domain for VSCALEF instructions.Craig Topper2017-02-261-0/+4
| | | | llvm-svn: 296286
* [AVX-512] Fix execution domain of scalar VRANGE/REDUCE/GETMANT with sae.Craig Topper2017-02-261-0/+1
| | | | llvm-svn: 296285
* [X86] Fix the execution domain for scalar SQRT intrinsic instruction.Craig Topper2017-02-263-7/+7
| | | | llvm-svn: 296284
* [X86] Add an additional CHECK prefix to a test. Some of the cases used it, ↵Craig Topper2017-02-261-12/+7
| | | | | | but it wasn't on the FileCheck command lines. llvm-svn: 296283
* [index] Add 'Parameter' symbol kind and 'Local' symbol property to ↵Argyrios Kyrtzidis2017-02-269-44/+98
| | | | | | | | | | | | distinguish function-local symbols Parameters have a 'child' relation to their function/method. Also add an option '-include-locals' to 'c-index-test core' to enable indexing of function-local symbols. Original patch from Nathan Hawes with some changes by me. https://reviews.llvm.org/D30304 llvm-svn: 296282
* [SCCP] Remove manual folding of terminator instructions.Xin Tong2017-02-261-26/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: BranchInst, SwitchInst (with non-default case) with Undef as input is not possible at this point. As we always default-fold terminator to one target in ResolvedUndefsIn and set the input accordingly. So we should only have constantint/blockaddress here. If ConstantFoldTerminator fails, that could mean 2 things. 1. ConstantFoldTerminator is doing something unexpected, i.e. not folding on constantint or blockaddress and not making blocks that should be dead dead. 2. This is not a terminator on constantint or blockaddress. Its on a constant or overdefined, then this block should not be dead. In both cases, we should assert. Reviewers: davide, efriedma, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30381 llvm-svn: 296281
* [X86] Clean up test/CodeGen/X86/2006-03-02-InstrSchedBug.llDavid L. Jones2017-02-261-8/+9
| | | | | | | | | | | | | | | Summary: Migrated from grep to FileCheck. Re-indented code, removed boilerplate comments. Added 'entry' label at beginning of basic block. Patch by Jorge Gorbe! Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30320 llvm-svn: 296280
* Revert "In visitSTORE, always use FindBetterChain, rather than only when ↵Nirav Dave2017-02-2674-2499/+2546
| | | | | | | | UseAA is enabled." This reverts commit r296252 until 256-bit operations are more efficiently generated in X86. llvm-svn: 296279
* Add a section about how to use ld.lld.Rui Ueyama2017-02-261-0/+23
| | | | llvm-svn: 296278
* vec perm can go down either pipeline on P8.Eric Christopher2017-02-261-1/+1
| | | | | | No observable changes, spotted while looking at the scheduling description. llvm-svn: 296277
* Update cxx_dr_status page.Richard Smith2017-02-251-3/+3
| | | | llvm-svn: 296276
* C++ DR1611, 1658, 2180: implement "potentially constructed subobject" rules ↵Richard Smith2017-02-2512-36/+354
| | | | | | | | | | | | | | | | | | | | | | for special member functions. Essentially, as a base class constructor does not construct virtual bases, such a constructor for an abstract class does not need the corresponding base class construction to be valid, and likewise for destructors. This creates an awkward situation: clang will sometimes generate references to the complete object and deleting destructors for an abstract class (it puts them in the construction vtable for a derived class). But we can't generate a "correct" version of these because we can't generate references to base class constructors any more (if they're template specializations, say, we might not have instantiated them and can't assume any other TU will emit a copy). Fortunately, we don't need to, since no correct program can ever invoke them, so instead emit symbols that just trap. We should stop emitting references to these symbols, but still need to emit definitions for compatibility. llvm-svn: 296275
* Fix signed-unsigned comparison warningSanjoy Das2017-02-251-1/+1
| | | | llvm-svn: 296274
* [ValueTracking] Don't do an unchecked shift in ComputeNumSignBitsSanjoy Das2017-02-253-2/+79
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously we used to return a bogus result, 0, for IR like `ashr %val, -1`. I've also added an assert checking that `ComputeNumSignBits` at least returns 1. That assert found an already checked in test case where we were returning a bad result for `ashr %val, -1`. Fixes PR32045. Reviewers: spatel, majnemer Reviewed By: spatel, majnemer Subscribers: efriedma, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D30311 llvm-svn: 296273
* [APInt] Add APInt::extractBits() method to extract APInt subrange (reapplied)Simon Pilgrim2017-02-255-8/+62
| | | | | | | | | | | | | | | | The current pattern for extract bits in range is typically: Mask.lshr(BitOffset).trunc(SubSizeInBits); Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation of memory for the temporary variable. This is another of the compile time issues identified in PR32037 (see also D30265). This patch adds the APInt::extractBits() helper method which avoids the temporary memory allocation. Differential Revision: https://reviews.llvm.org/D30336 llvm-svn: 296272
* [AVX-512] Fix the execution domain for scalar FMA instructions.Craig Topper2017-02-254-19/+20
| | | | llvm-svn: 296271
* [AVX-512] Fix the execution domain on some instructions.Craig Topper2017-02-254-11/+20
| | | | llvm-svn: 296270
* [AVX-512] Add an additional test case to show the execution domain for ↵Craig Topper2017-02-251-0/+12
| | | | | | vrqsrtsd is wrong. llvm-svn: 296269
* [AVX-512] Use update_llc_test_checks.py to regenerate the avx512er intrinsic ↵Craig Topper2017-02-251-23/+90
| | | | | | test. llvm-svn: 296268
* [test] Disable test/Index/pch-from-libclang.c for non-darwin systems.Argyrios Kyrtzidis2017-02-251-0/+4
| | | | llvm-svn: 296267
* reenable accidentally disabled test NFC.Nirav Dave2017-02-251-14/+14
| | | | llvm-svn: 296266
* [test] Use cc1 -triple for test/Index/pch-from-libclang.c.Argyrios Kyrtzidis2017-02-251-2/+2
| | | | | | Note quite sure why driver -target has no effect. llvm-svn: 296265
* [AVX-512] Remove unnecessary masked versions of VCVTSS2SD and VCVTSD2SS ↵Craig Topper2017-02-251-24/+11
| | | | | | using the scalar register class. We only have patterns for the masked intrinsics. llvm-svn: 296264
* [test] Add target to test/Index/pch-from-libclang.c.Argyrios Kyrtzidis2017-02-251-2/+2
| | | | | | Attempt to fix the failing bots. llvm-svn: 296263
* [driver] Pass a resource dir without the '/../' part.Argyrios Kyrtzidis2017-02-252-1/+20
| | | | | | | This get the resource dir string to match with the one from libclang (which is not adding '/../'), and allows clang to accept a modules-enabled PCH that was created by libclang. llvm-svn: 296262
* [modules] For -module-file-info, print out the resource dir path, since it ↵Argyrios Kyrtzidis2017-02-252-0/+2
| | | | | | is included in the module hash. llvm-svn: 296261
* [ExecutionDepsFix] Don't make copies of LiveReg objects when collecting ↵Craig Topper2017-02-252-13/+29
| | | | | | | | | | | | | | | | | | | | | | | operands for soft instructions Summary: While collecting operands we make copies of the LiveReg objects which are stored in the LiveRegs array. If the instruction uses the same register multiple times we end up with multiple copies. Later we iterate through the collected list of LiveReg objects and merge DomainValues. In the process of doing this the merge function can change the contents of the original LiveReg object in the LiveRegs array, but not the copies that have been made. So when we get to the second usage of the register we end up seeing a stale copy of the LiveReg object. To fix this I've stopped copying and now just store a pointer to the original LiveReg object. Another option might be to avoid adding the same register to the Regs array twice, but this approach seemed simpler. The included test case exposes this bug due to an AVX-512 masked OR instruction using the same register for the passthru operand and one of the inputs to the OR operation. Fixes PR30284. Reviewers: RKSimon, stoklund, MatzeB, spatel, myatsina Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30242 llvm-svn: 296260
* No need to copy the variable [NFC]Artyom Skrobov2017-02-251-2/+1
| | | | llvm-svn: 296259
* Revert r296215, "[PDB] General improvements to Stream library." and followings.NAKAMURA Takumi2017-02-2579-1971/+847
| | | | | | | | | | | | | | | | | r296215, "[PDB] General improvements to Stream library." r296217, "Disable BinaryStreamTest.StreamReaderObject temporarily." r296220, "Re-enable BinaryStreamTest.StreamReaderObject." r296244, "[PDB] Disable some tests that are breaking bots." r296249, "Add static_cast to silence -Wc++11-narrowing." std::errc::no_buffer_space should be used for OS-oriented errors for socket transmission. (Seek discussions around llvm/xray.) I could substitute s/no_buffer_space/others/g, but I revert whole them ATM. Could we define and use LLVM errors there? llvm-svn: 296258
* Update various test's codegen. NFCAmaury Sechet2017-02-252-10/+482
| | | | llvm-svn: 296257
* Also test OpenBSD/powerpc here for the various types expected to be the same ↵Brad Smith2017-02-251-0/+1
| | | | | | across archs. llvm-svn: 296256
* Add test for known bits in uaddo and saddo.Amaury Sechet2017-02-251-0/+54
| | | | llvm-svn: 296255
* The automatic CHECK: to CHECK-LABEL: conversion, back in 2013,Artyom Skrobov2017-02-251-7/+7
| | | | | | | had missed most labels in this test because they didn't end with a colon. llvm-svn: 296254
* [DebugInfo] Skip implicit_const attributes when dumping .debug_info. NFC.Victor Leschuk2017-02-251-0/+6
| | | | | | | | | | | When dumping .debug_info section we loop through all attributes mentioned in .debug_abbrev section and dump values using DWARFFormValue::extractValue(). We need to skip implicit_const attributes here as their values are not really located in .debug_info but directly in .debug_abbrev. This patch fixes triggered assert() in DWARFFormValue::extractValue() caused by trying to access implicit_const values from .debug_info. llvm-svn: 296253
* In visitSTORE, always use FindBetterChain, rather than only when UseAA is ↵Nirav Dave2017-02-2574-2546/+2499
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled. Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner. * Simplify Consecutive Merge Store Candidate Search Now that address aliasing is much less conservative, push through simplified store merging search and chain alias analysis which only checks for parallel stores through the chain subgraph. This is cleaner as the separation of non-interfering loads/stores from the store-merging logic. When merging stores search up the chain through a single load, and finds all possible stores by looking down from through a load and a TokenFactor to all stores visited. This improves the quality of the output SelectionDAG and the output Codegen (save perhaps for some ARM cases where we correctly constructs wider loads, but then promotes them to float operations which appear but requires more expensive constant generation). Some minor peephole optimizations to deal with improved SubDAG shapes (listed below) Additional Minor Changes: 1. Finishes removing unused AliasLoad code 2. Unifies the chain aggregation in the merged stores across code paths 3. Re-add the Store node to the worklist after calling SimplifyDemandedBits. 4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is arbitrary, but seems sufficient to not cause regressions in tests. 5. Remove Chain dependencies of Memory operations on CopyfromReg nodes as these are captured by data dependence 6. Forward loads-store values through tokenfactors containing {CopyToReg,CopyFromReg} Values. 7. Peephole to convert buildvector of extract_vector_elt to extract_subvector if possible (see CodeGen/AArch64/store-merge.ll) 8. Store merging for the ARM target is restricted to 32-bit as some in some contexts invalid 64-bit operations are being generated. This can be removed once appropriate checks are added. This finishes the change Matt Arsenault started in r246307 and jyknight's original patch. Many tests required some changes as memory operations are now reorderable, improving load-store forwarding. One test in particular is worth noting: CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store forwarding converts a load-store pair into a parallel store and a memory-realized bitcast of the same value. However, because we lose the sharing of the explicit and implicit store values we must create another local store. A similar transformation happens before SelectionDAG as well. Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle llvm-svn: 296252
* [Doc] Modernize programmers manualPiotr Padlewski2017-02-251-28/+21
| | | | | | | | | | | | | | Summary: Fixed bunch of for loops to range based for loop and bunch of rendundat types with auto. Reviewers: echristo, silvas, chandlerc Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D30338 llvm-svn: 296251
* Empty line. NFCIXin Tong2017-02-251-1/+0
| | | | llvm-svn: 296250
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