diff options
author | Craig Topper <craig.topper@gmail.com> | 2017-02-26 06:45:48 +0000 |
---|---|---|
committer | Craig Topper <craig.topper@gmail.com> | 2017-02-26 06:45:48 +0000 |
commit | 49ba3f54062754b760702bd893be595e5b5358e2 (patch) | |
tree | 282d1c270d0acfe0db6dcc2c4fab898c6fa8a022 | |
parent | 6bf9b809ce6406b979b83c3ef59309f3b52d8aeb (diff) | |
download | bcm5719-llvm-49ba3f54062754b760702bd893be595e5b5358e2.tar.gz bcm5719-llvm-49ba3f54062754b760702bd893be595e5b5358e2.zip |
[AVX-512] Disable the redundant patterns in the VPBROADCASTBr_Alt and VPBROADCASTWr_Alt instructions. NFC
llvm-svn: 296289
-rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 0d8db5abcb8..3f5433de423 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -963,39 +963,41 @@ def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src), (VBROADCASTSDZm addr:$src)>; multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _, + SDPatternOperator OpNode, RegisterClass SrcRC> { defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), (ins SrcRC:$src), "vpbroadcast"##_.Suffix, "$src", "$src", - (_.VT (X86VBroadcast SrcRC:$src))>, T8PD, EVEX; + (_.VT (OpNode SrcRC:$src))>, T8PD, EVEX; } multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _, + SDPatternOperator OpNode, RegisterClass SrcRC, Predicate prd> { let Predicates = [prd] in - defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512; + defm Z : avx512_int_broadcast_reg<opc, _.info512, OpNode, SrcRC>, EVEX_V512; let Predicates = [prd, HasVLX] in { - defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256; - defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128; + defm Z256 : avx512_int_broadcast_reg<opc, _.info256, OpNode, SrcRC>, EVEX_V256; + defm Z128 : avx512_int_broadcast_reg<opc, _.info128, OpNode, SrcRC>, EVEX_V128; } } let isCodeGenOnly = 1 in { -defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR8, - HasBWI>; -defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR16, - HasBWI>; +defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, + X86VBroadcast, GR8, HasBWI>; +defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, + X86VBroadcast, GR16, HasBWI>; } let isAsmParserOnly = 1 in { defm VPBROADCASTBr_Alt : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, - GR32, HasBWI>; + null_frag, GR32, HasBWI>; defm VPBROADCASTWr_Alt : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, - GR32, HasBWI>; + null_frag, GR32, HasBWI>; } -defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32, - HasAVX512>; -defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64, - HasAVX512>, VEX_W; +defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, + X86VBroadcast, GR32, HasAVX512>; +defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, + X86VBroadcast, GR64, HasAVX512>, VEX_W; def : Pat <(v16i32 (X86vzext VK16WM:$mask)), (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>; |