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* [X86][SSE] Add v8i16 shift test for 2 shift values that doesn't match basic b...Simon Pilgrim2018-07-021-0/+32
* [ValueTracking] allow undef elements when matching vector absSanjay Patel2018-07-022-36/+31
* Disable failing test on x86_64-pc-windows-gnu, see PR38006.Yaron Keren2018-07-021-1/+1
* [CodeGen] Make block removal order deterministic in CodeGenPrepareDavid Stenberg2018-07-021-3/+5
* Test commit accessBalazs Keri2018-07-021-1/+1
* [X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104Alex Bradbury2018-07-021-1/+1
* [ELF] - Cleanup error reporting code and cover with the test. NFC.George Rimar2018-07-022-2/+21
* [llvm-exegesis] Change how the native architecture is determinedJohn Brawn2018-07-022-2/+3
* [X86] Use addAliasForDirective to support the .word directive (reland)Alex Bradbury2018-07-021-25/+3
* Revert r336100Alex Bradbury2018-07-021-3/+25
* [SLPVectorizer] Remove nullptr early-outs from Instruction::ShuffleVector get...Simon Pilgrim2018-07-021-6/+0
* [InstCombine] adjust shuffle tests with IR flags; NFCSanjay Patel2018-07-021-4/+3
* [X86] Use addAliasForDirective to support the .word directiveAlex Bradbury2018-07-021-25/+3
* [llvm-exegesis] Delegate the decision of cycle counter name to the targetJohn Brawn2018-07-023-9/+16
* Recommit r328307: [IPSCCP] Use constant range information for comparisons of ...Florian Hahn2018-07-022-124/+123
* [ms] Fix mangling of char16_t and char32_t to be compatible with MSVC.Nico Weber2018-07-022-10/+36
* [InstCombine] add tests for shuffle-binop; NFCSanjay Patel2018-07-021-37/+256
* [SLPVectorizer] Fix alternate opcode + shuffle cost function to correct handl...Simon Pilgrim2018-07-022-7/+27
* [clangd] ClangdServer::codeComplete return CodeCompleteResult, not LSP struct.Sam McCall2018-07-029-174/+207
* [ELF] - Remove dead code. NFC.George Rimar2018-07-021-1/+0
* [SLPVectorizer] Only Alternate opcodes use ShuffleVector cases for getEntryCo...Simon Pilgrim2018-07-021-1/+5
* [AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector)Sander de Smalen2018-07-0213-0/+763
* [AArch64][SVE] Asm: Support for (saturating) vector INC/DEC instructions.Sander de Smalen2018-07-0237-0/+750
* [X86][BtVer2] Added Jaguar FPU Pipe0/1 uop counters to permit basic llvm-exeg...Simon Pilgrim2018-07-021-0/+2
* [OMPT] Use alloca() to force availability of frame pointerJoachim Protze2018-07-021-0/+4
* [OMPT] Add tests for runtime entry points from non-OpenMP threadsJoachim Protze2018-07-021-12/+53
* [OMPT] Add testcases for thread_begin and thread_end callbacksJoachim Protze2018-07-022-0/+72
* [OMPT] Provide the right thread_num for ancestor levelsJoachim Protze2018-07-022-3/+371
* [Mips][FastISel] Do not duplicate condition while lowering branchesPetar Jovanovic2018-07-022-4/+29
* Fix for r336080: Missing colon in REQUIRES linePhilip Pfaffe2018-07-021-1/+1
* [ELF] - Change dyn_cast to cast. NFC.George Rimar2018-07-021-1/+1
* [AArch64][SVE] Asm: Support for vector element compares (immediate).Sander de Smalen2018-07-0222-0/+704
* [polly-acc] change cl_get_* return types to 32/64bitPhilip Pfaffe2018-07-022-9/+107
* Reapply r334980 and r334983.Sander de Smalen2018-07-0248-110/+1126
* [NFC] Test that shows unprofitability of instcombine with bit rangesMax Kazantsev2018-07-021-0/+32
* [X86] Put some cases in switch statements back on one line to be more compact...Craig Topper2018-07-021-566/+186
* [llvm-exegesis][NFC] Cleanup useless braces.Clement Courbet2018-07-021-16/+8
* [X86] Remove FMA3Info DenseMap. Break into sorted tables that we can binary s...Craig Topper2018-07-024-234/+149
* [PowerPC] Don't make it as pre-inc candidate if displacement isn't 4's multip...QingShan Zhang2018-07-022-0/+137
* Implement strip.invariant.groupPiotr Padlewski2018-07-0221-48/+296
* Add an entry for rodata constant merge sections to the defaultEric Christopher2018-07-022-2/+7
* [X86] Fix a few test names in avx512-intrinsics-fast-isel.ll to match their c...Craig Topper2018-07-011-8/+8
* [X86] Remove the places that return nullptr from X86InstrInfo::commuteInstruc...Craig Topper2018-07-011-44/+10
* [SLPVectorizer] Call InstructionsState.isOpcodeOrAlt with Instruction instead...Simon Pilgrim2018-07-011-11/+9
* [SLPVectorizer] Replace sameOpcodeOrAlt with InstructionsState.isOpcodeOrAlt ...Simon Pilgrim2018-07-011-12/+10
* [asan] Fix deadlock issue on FreeBSD, caused by use of .preinit_array in rL32...Fangrui Song2018-07-012-4/+15
* [X86][Disassembler] Remove TYPE_BNDR from translateImmediate.Craig Topper2018-07-011-2/+0
* [InstCombine] add abs tests with undef elts; NFCSanjay Patel2018-07-011-0/+30
* [PatternMatch] allow undef elements in vectors with m_NegSanjay Patel2018-07-012-72/+50
* [SLPVectorizer] Use InstructionsState Op/Alt opcodes directly. NFCI.Simon Pilgrim2018-07-011-4/+2
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