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| author | Clement Courbet <courbet@google.com> | 2018-07-02 06:39:55 +0000 |
|---|---|---|
| committer | Clement Courbet <courbet@google.com> | 2018-07-02 06:39:55 +0000 |
| commit | a53349251c4469b4c162a6ea096425b309c7ecff (patch) | |
| tree | 560c05c3094648fc9ce401d050ec3eb031e1e164 | |
| parent | 0661f67296288ed54d8a7d582db0bf8ddac059b8 (diff) | |
| download | bcm5719-llvm-a53349251c4469b4c162a6ea096425b309c7ecff.tar.gz bcm5719-llvm-a53349251c4469b4c162a6ea096425b309c7ecff.zip | |
[llvm-exegesis][NFC] Cleanup useless braces.
llvm-svn: 336076
| -rw-r--r-- | llvm/tools/llvm-exegesis/lib/X86/Target.cpp | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp index 8b878e503de..594c48bbdba 100644 --- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp @@ -132,32 +132,24 @@ class ExegesisX86Target : public ExegesisTarget { std::vector<llvm::MCInst> setRegToConstant(unsigned Reg) const override { - if (llvm::X86::GR8RegClass.contains(Reg)) { + if (llvm::X86::GR8RegClass.contains(Reg)) return {llvm::MCInstBuilder(llvm::X86::MOV8ri).addReg(Reg).addImm(1)}; - } - if (llvm::X86::GR16RegClass.contains(Reg)) { + if (llvm::X86::GR16RegClass.contains(Reg)) return {llvm::MCInstBuilder(llvm::X86::MOV16ri).addReg(Reg).addImm(1)}; - } - if (llvm::X86::GR32RegClass.contains(Reg)) { + if (llvm::X86::GR32RegClass.contains(Reg)) return {llvm::MCInstBuilder(llvm::X86::MOV32ri).addReg(Reg).addImm(1)}; - } - if (llvm::X86::GR64RegClass.contains(Reg)) { + if (llvm::X86::GR64RegClass.contains(Reg)) return {llvm::MCInstBuilder(llvm::X86::MOV64ri32).addReg(Reg).addImm(1)}; - } - if (llvm::X86::VR128XRegClass.contains(Reg)) { + if (llvm::X86::VR128XRegClass.contains(Reg)) return setVectorRegToConstant(Reg, 16, llvm::X86::VMOVDQUrm); - } - if (llvm::X86::VR256XRegClass.contains(Reg)) { + if (llvm::X86::VR256XRegClass.contains(Reg)) return setVectorRegToConstant(Reg, 32, llvm::X86::VMOVDQUYrm); - } - if (llvm::X86::VR512RegClass.contains(Reg)) { + if (llvm::X86::VR512RegClass.contains(Reg)) return setVectorRegToConstant(Reg, 64, llvm::X86::VMOVDQU64Zrm); - } if (llvm::X86::RFP32RegClass.contains(Reg) || llvm::X86::RFP64RegClass.contains(Reg) || - llvm::X86::RFP80RegClass.contains(Reg)) { + llvm::X86::RFP80RegClass.contains(Reg)) return setVectorRegToConstant(Reg, 8, llvm::X86::LD_Fp64m); - } return {}; } |
