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* [NFC][Codegen][PowerPC] Autogenerate shift-cmp.ll testRoman Lebedev2019-06-041-23/+23
| | | | | | Being affected by upcoming patch llvm-svn: 362529
* [NFC][Codegen][AMDGPU] Autogenerate commute-shifts.ll testRoman Lebedev2019-06-041-3/+42
| | | | | | Being affected by upcoming patch llvm-svn: 362528
* [GWP-ASan] Configuration options [3].Mitch Phillips2019-06-045-0/+253
| | | | | | | | | | | | | | | | | | | | | Summary: See D60593 for further information. This patch introduces the configuration options for GWP-ASan. In general, we expect the supporting allocator to populate the options struct, and give that to GWP-ASan during initialisation. For allocators that are okay with pulling in sanitizer_common, we also provide an optional parser that populates the gwp_asan::Options struct with values provided in the GWP_ASAN_OPTIONS environment variable. This patch contains very little logic, and all of the testable components (i.e. the optional parser's internal logic) is tested as part of the sanitizer_common testbed. Reviewers: vlad.tsyrklevich, morehouse, jfb Reviewed By: morehouse Subscribers: dexonsmith, kubamracek, mgorny, #sanitizers, llvm-commits, vitalybuka Tags: #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D62698 llvm-svn: 362527
* [MACHO] Replaced calls to getStruct with getStructOrErr in functions ↵Alex Brachet2019-06-041-33/+88
| | | | | | returning Error or Expected or similar llvm-svn: 362526
* [libcxx] Add test to check min/max requirement to regular expressionLouis Dionne2019-06-041-0/+67
| | | | | | | | | | | This commit adds tests that repeated characters in regular expressions are within numeric limits, and that a <= b in a regex like `x{a,b}`. Thanks to Andrey Maksimov for the patch. Differential Revision: https://reviews.llvm.org/D62816 llvm-svn: 362525
* [x86] split 256-bit store of concatenated vectorsSanjay Patel2019-06-0425-845/+786
| | | | | | | | | | | | | | | | | | | | This shows up as a side issue to the main problem for the AVX target example from PR37428: https://bugs.llvm.org/show_bug.cgi?id=37428 - https://godbolt.org/z/7tpRa3 But as we can see in the pile of existing test diffs, it's actually a widespread problem that affects any AVX or later target. Apart from a couple of oddballs, I think these are all improvements for the reasons stated in the code comment: we do not want to enable YMM unnecessarily (avoid vzeroupper and frequency throttling) and some cores split 256-bit stores anyway. We could say that MergeConsecutiveStores() is going overboard on some of these examples, but that won't solve the problem completely. But that is a reason I'm proposing this as a lowering rather than a combine: we will infinite loop fighting the merge code if we try this earlier. Differential Revision: https://reviews.llvm.org/D62498 llvm-svn: 362524
* [AArch64][ELF] Add support for PLT decoding with BTI instructions presentPeter Smith2019-06-042-2/+65
| | | | | | | | | | | | | | | | | | | | | | Arm Architecture v8.5a introduces Branch Target Identification (BTI). When enabled all indirect branches must target a bti instruction of the appropriate form. As PLT sequences may sometimes be the target of an indirect branch and PLT[0] always is, a static linker may need to generate PLT sequences that contain "bti c" as the first instruction. In effect: bti c adrp x16, page offset to .got.plt ... Instead of: adrp x16, page offset to .got.plt ... At present the PLT decoding assumes the adrp will always be the first instruction. This patch adds support for a single "bti c" to prefix it. A test binary has been uploaded with such a PLT sequence. A forthcoming LLD patch will make heavy use of the PLT decoding code. Differential Revision: https://reviews.llvm.org/D62598 llvm-svn: 362523
* [WebAssembly] Add comment as follow-up to rL362276. NFC.Sam Clegg2019-06-041-1/+3
| | | | | | | | | | Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62824 llvm-svn: 362522
* [CodeGen][ObjC] Convert '[self alloc]' in a class method to a call toAkira Hatanaka2019-06-043-11/+67
| | | | | | | | | | | | | 'objc_alloc(self)' Also convert '[[self alloc] init]' in a class method to a call to 'objc_alloc_init(self)'. rdar://problem/50855121 Differential Revision: https://reviews.llvm.org/D62643 llvm-svn: 362521
* llvm-undname: Yet more coverage for error pathsNico Weber2019-06-042-3/+53
| | | | | | | | | | | | | | | | - For error returns in demangleSpecialTableNode(), demangleLocalStaticGuard(), RTTITypeDescriptor, demangleRttiBaseClassDescriptorNode(), demangleUnsigned(), demangleUntypedVariable() (via RttiBaseClassArray) - For ?_A and ?_P which are handled at early levels of the demangler but are not implemented in a later stage; this is now more obvious - Replace a "default:" with an explicit list of cases, to get -Wswitch check we list all cases llvm-svn: 362520
* [LVI][CVP] Add support for urem, srem and sdivNikita Popov2019-06-042-26/+13
| | | | | | | | | | | | | The underlying ConstantRange functionality has been added in D60952, D61207 and D61238, this just exposes it for LVI. I'm switching the code from using a whitelist to a blacklist, as we're down to one unsupported operation here (xor) and writing it this way seems more obvious :) Differential Revision: https://reviews.llvm.org/D62822 llvm-svn: 362519
* [Tests] Update a test to consistently use new pass manager and FileCheck the ↵Philip Reames2019-06-041-1/+1
| | | | | | result llvm-svn: 362518
* [clangd] Minor cleanup. NFCIlya Biryukov2019-06-041-1/+0
| | | | | | Removed unused using declaration from TweakTests.cpp llvm-svn: 362517
* [Tests] Autogen tests so that diffs for a future change are understandablePhilip Reames2019-06-042-29/+119
| | | | llvm-svn: 362516
* llvm-undname: Add coverage for startsWithLocalScopePattern()Nico Weber2019-06-041-0/+35
| | | | llvm-svn: 362515
* llvm-undname: More no-op changes to increase test coverageNico Weber2019-06-042-6/+30
| | | | | | | | | | - Add test coverage around invalid anon namespaces and for error paths in demanglePrimitiveType() and in demangleFullyQualifiedTypeName() - Use DEMANGLE_UNREACHABLE in two more unreachable places llvm-svn: 362514
* [llvm-symbolizer] Flush output on bad inputJames Henderson2019-06-043-2/+44
| | | | | | | | | | | | | | | | | | | | One way of using llvm-symbolizer is to interactively within a process write a line from a parent process to llvm-symbolizer's stdin, and then read the output, then write the next line, read, etc. This worked as long as all the lines were good. However, this didn't work prior to this patch if any of the inputs were bad inputs, because the output is not flushed after a bad input, meaning the parent process is sat waiting for output, whilst llvm-symbolizer is sat waiting for input. This patch flushes the output after every invocation of symbolizeInput when reading from stdin. It also removes unnecessary flushing when llvm-symbolizer is not reading addresses from stdin, which should give a slight performance boost in these situations. Reviewed by: ikudrin Differential Revision: https://reviews.llvm.org/D62371 llvm-svn: 362511
* [lldb] Fix out-of-bounds read after c3ea7c66fec021867e005ad1b02f3c7e80feaa85James Y Knight2019-06-041-1/+1
| | | | | | | | "Add support for mid-function epilogues on x86 that end in a non-local jump." Detected by asan. llvm-svn: 362510
* [PowerPC] P9 Scheduling Model: dispatching rule fixesJinsong Ji2019-06-045-330/+366
| | | | | | | | | | | | | | | | This is to address some of the problems in existing P9 resource modeling, especially about the dispatching rules. Instead of using a hypothetical DISPATCHER , we try to use the number of actual dispatch slots, and define SchedWriteRes to model dispatch rules, then update instruction classes according to dispatch rules. All the dispatch rules and instruction classes update are made according to POWER9 User Manual. Differential Revision: https://reviews.llvm.org/D61873 llvm-svn: 362509
* No longer reject inputs when using a locale that has grouping information ↵Marshall Clow2019-06-042-3/+5
| | | | | | _and_ the input has no grouping characters at all. We continue to reject cases when the input has grouping characters in the wrong place. Fixes PR#28704 llvm-svn: 362508
* [SelectionDAG][x86] limit post-legalization store merging by typeSanjay Patel2019-06-045-9/+15
| | | | | | | | | | | The proposal in D62498 showed that x86 would benefit from vector store splitting, but that may conflict with the generic DAG combiner's store merging transforms. Add memory type to the existing TLI hook that enables the merging transforms, so we can limit those changes to scalars only for x86. llvm-svn: 362507
* llvm-undname: Several behavior-preserving changes to increase coverageNico Weber2019-06-044-16/+38
| | | | | | | | | | | | | | | | | - Replace `Error = true` in a few branches that are truly unreachable with DEMANGLE_UNREACHABLE - Remove early return early in startsWithLocalScopePattern() because it's redundant with the next two early returns - Remove unreachable `case '0'` (it's handled in the branch below) - Remove an unused bool return - Add test coverage for several early error returns, mostly in array type parsing llvm-svn: 362506
* [OpenMP][libomptarget] Enable usage of unified memory for declare target ↵Gheorghe-Teodor Bercea2019-06-046-2/+39
| | | | | | | | | | | | | | | | | | link variables Summary: This patch enables the usage of a host variable on the device for declare target link variables when unified memory is available. Reviewers: ABataev, caomhin, grokos Reviewed By: grokos Subscribers: Hahnfeld, guansong, jdoerfert, openmp-commits Tags: #openmp Differential Revision: https://reviews.llvm.org/D60884 llvm-svn: 362505
* [X86][SSE] Pulled out (sub (xor X, M), M) 'ConditionalNegate' out pattern ↵Simon Pilgrim2019-06-041-49/+66
| | | | | | | | match code. NFCI. As discussed on D62777 - we should be able to use this in more SSE41+ cases as well but that requires us to separate it from the OR(AND(),ANDN()) matcher. llvm-svn: 362504
* [Support] make countLeadingZeros() countTrailingZeros() countLeadingOnes() ↵Shawn Landden2019-06-042-13/+13
| | | | | | | | | | | | and countTrailingOnes() return unsigned This matches APInt's versions of these functions, and there is no need for these to be size_t. (as well as __builtin_clzll()) Differential Revision: https://reviews.llvm.org/D60823 llvm-svn: 362503
* [x86] add test for store merging/splitting; NFCSanjay Patel2019-06-041-0/+126
| | | | | | This is a reduction of a test that would infinite loop with D62498. llvm-svn: 362502
* [SimplifyCFG] fix last commitShawn Landden2019-06-041-0/+3
| | | | llvm-svn: 362501
* [CMake] Move and add settings to Apple-lldb-base cache scriptStefan Granitz2019-06-042-3/+5
| | | | llvm-svn: 362500
* [SimplifyCFG] NFC; remove bogus test caseShawn Landden2019-06-041-26/+0
| | | | | | | | | | Even if one bit is defined, the code is not clear what it is suppose to do. The test wants to assert that some bits are undef, but that's not what the IR does and I don't think it's even possible to do that in any meaningful way. It was added in D12497, so @reames might want to double check. Differential Revision: https://reviews.llvm.org/D60859 llvm-svn: 362499
* gn build: Merge r362459Nico Weber2019-06-042-0/+2
| | | | llvm-svn: 362498
* [ELF] Suppress "STT_SECTION symbol should be defined" on .eh_frame, .debug*, ↵Fangrui Song2019-06-045-62/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .zdebug* and .gcc_except_table Summary: With -r or --emit-relocs, we warn `STT_SECTION symbol should be defined` on relocations to discarded section symbol. This was added as an error in rLLD319404, but was not so effective before D61583 (it turned the error to a warning). Relocations from .eh_frame .debug* .zdebug* .gcc_except_table to discarded .text are very common and somewhat expected. Don't warn/error on them. As a reference, ld.bfd has a similar logic in _bfd_elf_default_action_discarded() to allow these cases. Delete invalid-undef-section-symbol.test because what it intended to check is now covered by the updated comdat-discarded-reloc.s Delete relocatable-eh-frame.s because we allow relocations from .eh_frame as a special case now. Reviewers: grimar, phosek, ruiu, espindola Reviewed By: ruiu Subscribers: emaste, arichardson, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62840 llvm-svn: 362497
* [clangd] Also apply adjustArguments when returning fallback commandsKadir Cetinkaya2019-06-042-2/+6
| | | | | | | | | | | | Reviewers: ilya-biryukov Subscribers: MaskRay, jkorous, arphaman, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D62856 llvm-svn: 362496
* Include what you use in PPCRegisterInfo.cppDmitri Gribenko2019-06-041-1/+0
| | | | llvm-svn: 362495
* [NFC][Codegen] D62818 - also add tests with X being constantRoman Lebedev2019-06-046-4/+452
| | | | | | | For X86, these may be a 'BT' pattern, and in general, can cause the transform to deadlock. llvm-svn: 362494
* [AArch64][ELF][llvm-readobj] Add support for BTI and PAC dynamic tagsPeter Smith2019-06-047-15/+217
| | | | | | | | | | | | | | | | | | | | | | | ELF for the 64-bit Arm Architecture defines two processor-specific dynamic tags: DT_AARCH64_BTI_PLT 0x70000001, d_val DT_AARCH64_PAC_PLT 0x70000003, d_val These presence of these tags indicate that PLT sequences have been protected using Branch Target Identification and Pointer Authentication respectively. The presence of both indicates that the PLT sequences have been protected with both Branch Target Identification and Pointer Authentication. This patch adds the tags and tests for llvm-readobj and yaml2obj. As some of the processor specific dynamic tags overlap, this patch splits them up, keeping their original default value if they were not previously mentioned explicitly in a switch case. Differential Revision: https://reviews.llvm.org/D62596 llvm-svn: 362493
* Unbreak my hasty "unbreak" cmake fixDavid Zarzycki2019-06-041-1/+1
| | | | llvm-svn: 362492
* Fix -Wparentheses warning. NFCI.Simon Pilgrim2019-06-041-2/+2
| | | | llvm-svn: 362491
* [AARCH64][ELF][llvm-readobj] Support for AArch64 .note.gnu.propertyPeter Smith2019-06-043-3/+55
| | | | | | | | | | | | | | | | | | ELF for the 64-bit Arm Architecture defines a processor specific property type GNU_PROPERTY_AARCH64_FEATURE_1_AND as GNU_PROPERTY_LOPROC. This property works in a similar way to the existing X86 processor specific property GNU_PROPERTY_GNU_X86_FEATURE_1_AND. Two feature bits are defined for GNU_PROPERTY_AARCH64_FEATURE_1_AND: - GNU_PROPERTY_AARCH64_FEATURE_1_BTI 0x1 - GNU_PROPERTY_AARCH64_FEATURE_1_PAC 0x2 This patch defines the property, feature bits and implements support for printing in llvm-readobj. Differential Revision: https://reviews.llvm.org/D62595 llvm-svn: 362490
* Fix Wshadow warningSimon Pilgrim2019-06-041-2/+2
| | | | llvm-svn: 362489
* [DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold ↵Roman Lebedev2019-06-048-63/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | (PR41952) Summary: This *might* be the last fold for `sink-addsub-of-const.ll`, but i'm not sure yet. As far as i can tell, there are no regressions here (ignoring x86-32), all changes are either good or neutral. This, almost surprisingly to me, fixes the motivational tests (in `shift-amount-mod.ll`) `@reg32_lshr_by_sub_from_negated` from [[ https://bugs.llvm.org/show_bug.cgi?id=41952 | PR41952 ]]. https://rise4fun.com/Alive/vMd3 Reviewers: RKSimon, t.p.northover, craig.topper, spatel, efriedma Reviewed By: RKSimon Subscribers: sdardis, javed.absar, arichardson, kristof.beyls, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62774 llvm-svn: 362488
* [DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C foldRoman Lebedev2019-06-046-92/+129
| | | | | | | | | | | | | | | | | | | | | Summary: All changes except ARM look **great**. https://rise4fun.com/Alive/R2M The regression `test/CodeGen/ARM/addsubcarry-promotion.ll` is recovered fully by D62392 + D62450. Reviewers: RKSimon, craig.topper, spatel, rogfer01, efriedma Reviewed By: efriedma Subscribers: dmgreen, javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62266 llvm-svn: 362487
* [SelectionDAG] ComputeNumSignBits - support constant pool values from targetSimon Pilgrim2019-06-042-26/+52
| | | | | | | | | | | | As I mentioned on D61887 we don't get many hits on ComputeNumSignBits as we did on computeKnownBits. The case we do get is interesting though - it allows us to use the 'ConditionalNegate' combine in combineLogicBlendIntoPBLENDV to remove a select. It comes too late for SSE41 (BLENDV) cases, but SSE2 tests can hit it now. We should probably try to make use of this for SSE41+ targets as well - avoiding variable blends is usually a good idea. I'll investigate as a followup. Differential Revision: https://reviews.llvm.org/D62777 llvm-svn: 362486
* [SelectionDAG] ComputeNumSignBits - clang-format + improve *EXTLOAD ↵Simon Pilgrim2019-06-041-7/+7
| | | | | | | | comments. NFCI. Pre-commit requested for D62777. llvm-svn: 362485
* [llvm-ar] Reapply Fix relative thin archive path handlingOwen Reynolds2019-06-048-37/+134
| | | | | | | | | | Includes a fix for an introduced build failure due to a post c++11 use of std::mismatch. This fixes some thin archive relative path issues, paths are shortened where possible and paths are output correctly when using the display table command. Differential Revision: https://reviews.llvm.org/D59491 llvm-svn: 362484
* [SelectionDAG] Add fpto[us]i(undef) --> undef constant foldSimon Pilgrim2019-06-044-4/+13
| | | | | | | | Follow up to D62807. Differential Revision: https://reviews.llvm.org/D62811 llvm-svn: 362483
* [ARM] Add FP16 vector insert/extract patternsMikhail Maltsev2019-06-043-0/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds two FP16 extraction and two insertion patterns (one per possible vector length). Extractions are handled by copying a Q/D register into one of VFP2 class registers, where single FP32 sub-registers can be accessed. Then the extraction of even lanes are simple sub-register extractions (because we don't care about the top parts of registers for FP16 operations). Odd lanes need an additional VMOVX instruction. Unfortunately, insertions cannot be handled in the same way, because: * There is no instruction to insert FP16 into an even lane (VINS only works with odd lanes) * The patterns for odd lanes will have a form of a DAG (not a tree), and will not be implementable in pure tablegen Because of this insertions are handled in the same way as 16-bit integer insertions (with conversions between FP registers and GPRs using VMOVHR instructions). Without these patterns the ARM backend would sometimes fail during instruction selection. This patch also adds patterns which combine: * an FP16 element extraction and a store into a single VST1 instruction * an FP16 load and insertion into a single VLD1 instruction Differential Revision: https://reviews.llvm.org/D62651 llvm-svn: 362482
* [clangd] Support offsets for parameters in signatureHelpIlya Biryukov2019-06-047-123/+213
| | | | | | | | | | | | | | | | Summary: Added to LSP in version 3.14 Reviewers: hokein Reviewed By: hokein Subscribers: MaskRay, jkorous, arphaman, kadircet, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D62476 llvm-svn: 362481
* Silenced a warning "implicit conversion turns string literal into bool" ↵Dmitri Gribenko2019-06-041-2/+3
| | | | | | introduced in r362473 llvm-svn: 362480
* [CodeComplete] Include more text into typed chunks of pattern completionsIlya Biryukov2019-06-044-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | Summary: To allow filtering on any of the words in the editors. In particular, the following completions were changed: - 'using namespace <#name#>' Typed text before: 'using', after: 'using namespace'. - 'else if (#<condition#>)' Before: 'else', after: 'else if'. - 'using typename <#qualifier#>::<#name#>' Before: 'using', after: 'using typename'. Reviewers: sammccall Reviewed By: sammccall Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D62615 llvm-svn: 362479
* [HWASAN] Make new/delete weakEugene Leviant2019-06-042-8/+31
| | | | | | | | | This allows instrumenting programs which have their own versions of new and delete operators. Differential revision: https://reviews.llvm.org/D62794 llvm-svn: 362478
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