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* [LoopVectorizer] give more advice in remark about failure to vectorize callSanjay Patel2019-01-122-3/+75
| | | | | | | | | | Something like this is requested by: https://bugs.llvm.org/show_bug.cgi?id=40265 ...and it seems like a common enough case that we should acknowledge it. Differential Revision: https://reviews.llvm.org/D56551 llvm-svn: 351010
* [Algorithm] Add make_const_ref corresponding to make_const_ptrStephen Kelly2019-01-121-0/+6
| | | | | | | | | | Reviewers: aaron.ballman Subscribers: dexonsmith, kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D56622 llvm-svn: 351009
* [DAGCombiner] fold insert_subvector of insert_subvectorSanjay Patel2019-01-123-100/+108
| | | | | | | | | | | | | | | | | | | This pattern: t33: v8i32 = insert_subvector undef:v8i32, t35, Constant:i64<0> t21: v16i32 = insert_subvector undef:v16i32, t33, Constant:i64<0> ...shows up in PR33758: https://bugs.llvm.org/show_bug.cgi?id=33758 ...although this patch doesn't make any difference to the final result on that yet. In the affected tests here, it looks like it just makes RA wiggle. But we might as well squash this to prevent it interfering with other pattern-matching. Differential Revision: https://reviews.llvm.org/D56604 llvm-svn: 351008
* [analyzer] Fix unused variable warnings in Release buildsBenjamin Kramer2019-01-121-5/+2
| | | | | | This was just an inlined version of isa<CXXConstructExpr>. NFC. llvm-svn: 351007
* [llvm-objdump] - Change the output for --all-headers.George Rimar2019-01-122-5/+25
| | | | | | | | | | | This is for https://bugs.llvm.org/show_bug.cgi?id=40008, it starts printing the file headers when --all-headers is given and do a minor cosmetic change. Differential revision: https://reviews.llvm.org/D56588 llvm-svn: 351006
* Use getShiftAmountTy for shift amounts.Simon Pilgrim2019-01-121-1/+2
| | | | llvm-svn: 351005
* gn build: Unbreak Windows buildNico Weber2019-01-122-3/+3
| | | | | | | | | | | | I didn't break all that much during upstreaming, just needs two small fixes: - fix spelling of MCJITTests.def file - make libLTO a shared_library to put it in bin/ on Windows where it is in the CMake build too Differential Revision: https://reviews.llvm.org/D56630 llvm-svn: 351004
* [X86] Add more usub.sat vector tests; NFCNikita Popov2019-01-121-143/+1560
| | | | | | Add additional vXi32 and vXi64 tests. llvm-svn: 351003
* [NetBSD] Enable additional sanitizer typesMichal Gorny2019-01-122-8/+51
| | | | | | Differential Revision: https://reviews.llvm.org/D56607 llvm-svn: 351002
* [ORC][MIPS] Fill delay-slot after `jr` instructionSimon Atanasyan2019-01-121-5/+5
| | | | | | | | | | MIPS `jr` instruction uses a delay-slot. To escape execution of arbitrary instruction we should either fill the delay-slot by `nop` instruction or swap `jr` instruction and logically preceding instruction. This fix implements the second method to generate a bit more effective code. llvm-svn: 351001
* [ORC][MIPS] Setup t9 register and call function through this registerSimon Atanasyan2019-01-122-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS ABI states that every function must be called through jalr $t9. In other words, a function expect that t9 register points to the beginning of its code. A function uses this register to calculate offset to the Global Offset Table and save it to the `gp` register. ``` lui $gp, %hi(_gp_disp) addiu $gp, %lo(_gp_disp) addu $gp, $gp, $t9 ``` If `t9` and as a result `$gp` point to the wrong place the following code loads incorrect value from GOT and passes control to invalid code. ``` lw $v0,%call16(foo)($gp) jalr $t9 ``` OrcMips32 and OrcMips64 writeResolverCode methods pass control to the resolved address, but do not setup `$t9` before the call. The `t9` holds value of the beginning of `resolver` code so any attempts to call routines via GOT failed. This change fixes the problem. The `OrcLazy/hidden-visibility.ll` test starts to pass correctly. Before the change it fails on MIPS because the `exitOnLazyCallThroughFailure` called from the resolver code could not call libc routine `exit` via GOT. Differential Revision: http://reviews.llvm.org/D56058 llvm-svn: 351000
* [X86] Improve vXi64 ISD::ABS codegen with SSE41+Simon Pilgrim2019-01-123-135/+263
| | | | | | | | Make use of vblendvpd to select on the signbit Differential Revision: https://reviews.llvm.org/D56544 llvm-svn: 350999
* [X86][AARCH64] Improve ISD::ABS supportSimon Pilgrim2019-01-128-29/+85
| | | | | | | | This patch takes some of the code from D49837 to allow us to enable ISD::ABS support for all SSE vector types. Differential Revision: https://reviews.llvm.org/D56544 llvm-svn: 350998
* Reapply "[DemandedBits] Use SetVector for Worklist"Nikita Popov2019-01-121-7/+6
| | | | | | | | | | | | | | | | DemandedBits currently uses a simple vector for the worklist, which means that instructions may be inserted multiple times into it. Especially in combination with the deep lattice, this may cause instructions too be recomputed very often. To avoid this, switch to a SetVector. Reapplying with a smaller number of inline elements in the SmallSetVector, to avoid running into the SmallDenseMap issue described in D56455. Differential Revision: https://reviews.llvm.org/D56362 llvm-svn: 350997
* [llvm-objcopy] [COFF] Remove pointless Reader/Writer base classes. NFC.Martin Storsjo2019-01-124-24/+5
| | | | | | | | | These were copied as part of the original design from the ELF backend, but aren't necessary at the moment. Differential Revision: https://reviews.llvm.org/D56431 llvm-svn: 350996
* [X86] Remove X86ISD::SELECT as its no longer used by any of our intrinsic ↵Craig Topper2019-01-123-3/+1
| | | | | | lowering. llvm-svn: 350995
* [X86] Add ISD node for masked version of CVTPS2PH.Craig Topper2019-01-127-39/+76
| | | | | | | | | | The 128-bit input produces 64-bits of output and fills the upper 64-bits with 0. The mask only applies to the lower elements. But we can't represent this with a vselect like we normally do. This also avoids the need to have a special X86ISD::SELECT when avx512bw isn't enabled since vselect v8i16 isn't legal there. Fixes another instruction for PR34877. llvm-svn: 350994
* [RISCV] Introduce codegen patterns for RV64M-only instructionsAlex Bradbury2019-01-126-9/+1781
| | | | | | | | | | | | | | | | | | As discussed on llvm-dev <http://lists.llvm.org/pipermail/llvm-dev/2018-December/128497.html>, we have to be careful when trying to select the *w RV64M instructions. i32 is not a legal type for RV64 in the RISC-V backend, so operations have been promoted by the time they reach instruction selection. Information about whether the operation was originally a 32-bit operations has been lost, and it's easy to write incorrect patterns. Similarly to the variable 32-bit shifts, a DAG combine on ANY_EXTEND will produce a SIGN_EXTEND if this is likely to result in sdiv/udiv/urem being selected (and so save instructions to sext/zext the input operands). Differential Revision: https://reviews.llvm.org/D53230 llvm-svn: 350993
* [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructionsAlex Bradbury2019-01-125-185/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | This restores support for selecting the SLLW/SRLW/SRAW instructions, which was removed in rL348067 as the previous patterns made some unsafe assumptions. Also see the related llvm-dev discussion <http://lists.llvm.org/pipermail/llvm-dev/2018-December/128497.html> Ultimately I didn't introduce a custom SelectionDAG node, but instead added a DAG combine that inserts an AssertZext i5 on the shift amount for an i32 variable-length shift and also added an ANY_EXTEND DAG-combine which will instead produce a SIGN_EXTEND for an i32 variable-length shift, increasing the opportunity to safely select SLLW/SRLW/SRAW. There are obviously different ways of addressing this (a number discussed in the llvm-dev thread), so I'd welcome further feedback and comments. Note that there are now some cases in test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll where sraw/srlw/sllw is selected even though sra/srl/sll could be used without any extra instructions. Given both are semantically equivalent, there doesn't seem a good reason to prefer one vs the other. Given that would require more logic to still select sra/srl/sll in those cases, I've left it preferring the *w variants. Differential Revision: https://reviews.llvm.org/D56264 llvm-svn: 350992
* [X86] Remove unnecessary code from getMaskNode.Craig Topper2019-01-121-5/+1
| | | | | | We no longer need to extend mask scalars before bitcasting them to vXi1. This was only needed for the truncate intrinsics. And was really a bug in our lowering of them. llvm-svn: 350991
* Add SymbolFileBreakpad.Jason Molenda2019-01-121-0/+15
| | | | llvm-svn: 350990
* [X86] When lowering v1i1/v2i1/v4i1/v8i1 load/store with avx512f, but not ↵Craig Topper2019-01-128-247/+119
| | | | | | | | | | avx512dq, use v16i1 as the intermediate mask type instead of v8i1. We still use i8 for the load/store type. So we need to convert to/from i16 to around the mask type. By doing this we get an i8->i16 extload which we can then pattern match to a KMOVW if the access is aligned. llvm-svn: 350989
* [X86] Change some patterns that select MOVZX16rm8 to instead select ↵Craig Topper2019-01-121-3/+6
| | | | | | | | MOVZX32rm8 and extract the subregister. This should be a shorter encoding and is consistent with what we do for zext i8->i16 llvm-svn: 350988
* [ARM] Fix typoEvandro Menezes2019-01-121-1/+0
| | | | | | Fix typo in r350952. llvm-svn: 350986
* [X86] Add ISD nodes for masked truncate so we can properly represent when ↵Craig Topper2019-01-129-452/+614
| | | | | | | | | | | | the output has more elements than the input due to needing to be 128 bits. We can't properly represent this with a vselect since the upper elements of the result are supposed to be zeroed regardless of the mask. This also reuses the new nodes even when the result type fits in 128 bits if the input is q/d and the result is w/b since vselect w/b using k-register condition isn't legal without avx512bw. Currently we're doing this even when avx512bw is enabled, but I might change that. This fixes some of PR34877 llvm-svn: 350985
* NFC: Port loop to cxx_range_forStephen Kelly2019-01-121-3/+2
| | | | llvm-svn: 350984
* [sanitizer] Move android's GetPageSize to a header (NFC)Evgeniy Stepanov2019-01-122-4/+13
| | | | | | | No need to pay function call overhead for a function that returns a constant. llvm-svn: 350983
* [analyzer] Support for OSObjects out parameters in RetainCountCheckerGeorge Karpenkov2019-01-117-83/+413
| | | | | | | | | rdar://46357478 rdar://47121327 Differential Revision: https://reviews.llvm.org/D56240 llvm-svn: 350982
* [analyzer] Introduce a convenience method for getting a CallEvent from an ↵George Karpenkov2019-01-112-22/+37
| | | | | | | | arbitrary Stmt Differential Revision: https://reviews.llvm.org/D56300 llvm-svn: 350981
* sanitizer_common: Change gen_dynamic_list.py to take a -o argument instead ↵Peter Collingbourne2019-01-112-12/+15
| | | | | | | | | | | of writing to stdout. This makes the script a little more gn friendly; gn does not support redirecting the output of a script. Differential Revision: https://reviews.llvm.org/D56579 llvm-svn: 350980
* gn build: Add a stage2 toolchain for Android.Peter Collingbourne2019-01-116-28/+96
| | | | | | | | | This makes it possible to build llvm-symbolizer for Android, which is one of the prerequisites for running the sanitizer tests on Android. Differential Revision: https://reviews.llvm.org/D56577 llvm-svn: 350979
* [lldbsuite] Skip TestExitDuringStep on WindowsStella Stamenova2019-01-111-0/+1
| | | | | | This test is flaky on Windows and will occasionally hang or fail. llvm-svn: 350978
* gn build: Create a template for unix toolchains.Peter Collingbourne2019-01-111-96/+112
| | | | | | | | | | Also change the toolchain description to use current_os instead of host_os so that the template can be used for cross builds, and add a current_os to the win toolchain to match the unix toolchain. Differential Revision: https://reviews.llvm.org/D56576 llvm-svn: 350977
* [AArch64] Improve Exynos predicatesEvandro Menezes2019-01-111-3/+12
| | | | | | | Expand the predicate using shifted arithmetic and logic instructions to also consider the respective not shifted instructions. llvm-svn: 350976
* Add a release note about MSP430 support.Rui Ueyama2019-01-111-0/+2
| | | | llvm-svn: 350975
* gn build: Merge r350958.Peter Collingbourne2019-01-112-3/+13
| | | | llvm-svn: 350974
* [CMake] Fix standalone build after LLVM exports utility targetsStefan Granitz2019-01-111-2/+0
| | | | | | | LLVM started exporting targets for utilites with https://reviews.llvm.org/rL350959, which broke compiler-rt standalone builds because it was used to define FileCheck manually. Changed this, so FileCheck gets imported now. llvm-svn: 350973
* Change from a to a . Fixes PR#39871.Marshall Clow2019-01-117-23/+23
| | | | llvm-svn: 350972
* [ConstantFolding] Fold undef for integer intrinsicsNikita Popov2019-01-116-594/+174
| | | | | | | | | | | | | | | | | | | This fixes https://bugs.llvm.org/show_bug.cgi?id=40110. This implements handling of undef operands for integer intrinsics in ConstantFolding, in particular for the bitcounting intrinsics (ctpop, cttz, ctlz), the with.overflow intrinsics, the saturating math intrinsics and the funnel shift intrinsics. The undef behavior follows what InstSimplify does for the general cas e of non-constant operands. For the bitcount intrinsics (where InstSimplify doesn't do undef handling -- there cannot be a combination of an undef + non-constant operand) I'm using a 0 result if the intrinsic is defined for zero and undef otherwise. Differential Revision: https://reviews.llvm.org/D55950 llvm-svn: 350971
* [Darwin][Driver] Don't pass a file as object_path_lto during ThinLTOSteven Wu2019-01-114-7/+40
| | | | | | | | | | | | | | | | | | | | | | Summary: After r327851, Driver::GetTemporaryPath will create the file rather than just create a potientially unqine filename. If clang driver pass the file as parameter as -object_path_lto, ld64 will pass it back to libLTO as GeneratedObjectsDirectory, which is going to cause a LLVM ERROR if it is not a directory. Now during thinLTO, pass a temp directory path to linker instread. rdar://problem/47194182 Reviewers: arphaman, dexonsmith Reviewed By: arphaman Subscribers: mehdi_amini, inglorion, jkorous, cfe-commits Differential Revision: https://reviews.llvm.org/D56608 llvm-svn: 350970
* [SLP]Moved NVPTX test under NVPTX directory, NFC.Alexey Bataev2019-01-111-0/+0
| | | | llvm-svn: 350969
* Fix unchecked Error introduced in r350956Alexandre Ganea2019-01-111-1/+3
| | | | llvm-svn: 350968
* [SLP]Update test checks for the SPL vectorizer, NFC.Alexey Bataev2019-01-1181-692/+3578
| | | | llvm-svn: 350967
* [X86] Fix incomplete handling of register-assigned variables in parsing.Nirav Dave2019-01-114-188/+647
| | | | | | | | | | | | | | Teach x86 assembly operand parsing to distinguish between assembler variable assigned to named registers and those assigned to immediate values. Reviewers: rnk, nickdesaulniers, void Subscribers: hiraditya, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D56287 llvm-svn: 350966
* [Sanitizer] Disable getusershell interception for AndroidDavid Carlier2019-01-112-2/+2
| | | | | | | | | | Reviewers: vitalybuka, pcc, eugenis Reviewed By: eugenis Differential Revision: https://reviews.llvm.org/D56583 llvm-svn: 350965
* gn build: Create a variable for the host toolchain and start using it in the ↵Peter Collingbourne2019-01-113-4/+5
| | | | | | | | tblgen template. Differential Revision: https://reviews.llvm.org/D56575 llvm-svn: 350964
* gn build: s/root_out_dir/root_build_dir/g in ↵Peter Collingbourne2019-01-111-2/+2
| | | | | | | | | | llvm/utils/gn/build/write_cmake_config.gni. This makes the generated files go to the right place when using a non-default toolchain. Differential Revision: https://reviews.llvm.org/D56427 llvm-svn: 350963
* [RISCV][NFC] Add CHECK lines for atomic operations on RV64IAlex Bradbury2019-01-114-0/+5770
| | | | | | | As or RV32I, we include these for completeness. Committing now to make it easier to review the RV64A patch. llvm-svn: 350962
* [llvm-mca] Update tests for Exynos (NFC)Evandro Menezes2019-01-114-0/+46
| | | | | | Update test cases for Exynos M4. llvm-svn: 350961
* [AArch64] Add pipeline model for Exynos M4Evandro Menezes2019-01-112-1/+1006
| | | | | | Add the scheduling and cost model for Exynos M4. llvm-svn: 350960
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