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| author | Evandro Menezes <e.menezes@samsung.com> | 2019-01-11 22:39:47 +0000 |
|---|---|---|
| committer | Evandro Menezes <e.menezes@samsung.com> | 2019-01-11 22:39:47 +0000 |
| commit | 7d7e3256cd8f935a370bc289e2752b0a3efe073a (patch) | |
| tree | a2b8e1280a731280b6148a0916afd9176e3d8cee | |
| parent | 4f194250ecaf5f539df55dd896c73d7ca43634b6 (diff) | |
| download | bcm5719-llvm-7d7e3256cd8f935a370bc289e2752b0a3efe073a.tar.gz bcm5719-llvm-7d7e3256cd8f935a370bc289e2752b0a3efe073a.zip | |
[AArch64] Improve Exynos predicates
Expand the predicate using shifted arithmetic and logic instructions to also
consider the respective not shifted instructions.
llvm-svn: 350976
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedPredExynos.td | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td index 2044e30ec1c..48c54230e9d 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredExynos.td @@ -48,7 +48,10 @@ def ExynosArithFn : TIIPredicate< CheckExtBy3]>]>]>>>, MCOpcodeSwitchCase< IsArithShiftOp.ValidOpcodes, - MCReturnStatement<ExynosCheckShift>>], + MCReturnStatement<ExynosCheckShift>>, + MCOpcodeSwitchCase< + IsArithUnshiftOp.ValidOpcodes, + MCReturnStatement<TruePred>>], MCReturnStatement<FalsePred>>>; def ExynosArithPred : MCSchedPredicate<ExynosArithFn>; @@ -58,7 +61,10 @@ def ExynosLogicFn : TIIPredicate< MCOpcodeSwitchStatement< [MCOpcodeSwitchCase< IsLogicShiftOp.ValidOpcodes, - MCReturnStatement<ExynosCheckShift>>], + MCReturnStatement<ExynosCheckShift>>, + MCOpcodeSwitchCase< + IsLogicUnshiftOp.ValidOpcodes, + MCReturnStatement<TruePred>>], MCReturnStatement<FalsePred>>>; def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>; @@ -73,7 +79,10 @@ def ExynosLogicExFn : TIIPredicate< [ExynosCheckShift, CheckAll< [CheckShiftLSL, - CheckShiftBy8]>]>>>], + CheckShiftBy8]>]>>>, + MCOpcodeSwitchCase< + IsLogicUnshiftOp.ValidOpcodes, + MCReturnStatement<TruePred>>], MCReturnStatement<FalsePred>>>; def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>; |
