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* [DAGCombiner] When combining zero_extend of a truncate, only mask before ↵Craig Topper2018-03-0117-92/+70
| | | | | | | | | | extending for vectors. Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code. Differential Revision: https://reviews.llvm.org/D42679 llvm-svn: 326500
* [Driver] Pass -f[no-]emulated-tls and set up ExplicitEmulatedTLSChih-Hung Hsieh2018-03-016-17/+54
| | | | | | | | | | Since LLVM r326341, default EmulatedTLS mode is decided in backend according to target triple. Any front-end should pass -f[no]-emulated-tls to backend and set up ExplicitEmulatedTLS only when the flags are used. Differential Revision: https://reviews.llvm.org/D43965 llvm-svn: 326499
* Don't ingoned --enable-new-dtags.Rafael Espindola2018-03-012-2/+7
| | | | llvm-svn: 326498
* [X86][MMX] Improve handling of 64-bit MMX constantsSimon Pilgrim2018-03-014-30/+33
| | | | | | | | | | | | 64-bit MMX constant generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type. This patch bitcasts the constant to a double value to allow correct loading directly to the MMX register. I've added MMX constant asm comment support to improve testing, it's better to always print the double values as hex constants as MMX is mainly an integer unit (and even with 3DNow! its just floats). Differential Revision: https://reviews.llvm.org/D43616 llvm-svn: 326497
* [modules] Don't diagnose "redefinition" of a friend with a pending definitionRichard Smith2018-03-012-0/+48
| | | | | | if the other definition is a merged copy of the same function. llvm-svn: 326496
* [SelectionDAG] Support some SimplifySetCC cases for comparing against vector ↵Craig Topper2018-03-013-53/+36
| | | | | | | | | | | | | | splats of constants. This supports things like (setcc ugt X, 0) -> (setcc ne X, 0) I've restricted to only make changes to vectors before legalize ops because I doubt all targets have accurate condition code legality information for vectors given how little we did before. Differential Revision: https://reviews.llvm.org/D42948 llvm-svn: 326495
* [X86][AVX] Add v2f32 <-> v2i8/v2i16/v2i32 vector testsSimon Pilgrim2018-03-011-0/+342
| | | | llvm-svn: 326494
* [www] Capitalize "Clang" when referring to the project, and generalize theRichard Smith2018-03-012-22/+24
| | | | | | | | introduction on the front page page. We still use the lowercase "clang" spelling when referring to the driver binary. llvm-svn: 326493
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-016-1/+73
| | | | llvm-svn: 326492
* Add an llc testcase analogous to test/LTO/X86/strip-debug-info.llAdrian Prantl2018-03-011-0/+22
| | | | | | rdar://problem/37963669 llvm-svn: 326491
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtzMatt Arsenault2018-03-012-1/+79
| | | | | | Patch by Tom Stellard llvm-svn: 326490
* AMDGPU/GlobalISel: Define instruction mapping for G_ORMatt Arsenault2018-03-013-0/+125
| | | | | | Patch by Tom Stellard llvm-svn: 326489
* [X86][SSE] Regenerate float to/from i8/i16 vector testsSimon Pilgrim2018-03-011-20/+238
| | | | llvm-svn: 326488
* AMDGPU/GlobalISel: Remove default register mappingMatt Arsenault2018-03-011-16/+1
| | | | | | | | | This crashes for some opcodes, which prevents the SelectionDAG fallback from working. Patch by Tom Stellard llvm-svn: 326487
* [AArch64] Clean up code (NFC)Evandro Menezes2018-03-011-16/+13
| | | | | | | Clean up a couple of functions in `AArch64TargetLowering` by removing redundant statements. llvm-svn: 326486
* Added P0805 to the list of ready bitsMarshall Clow2018-03-011-2/+3
| | | | llvm-svn: 326485
* [X86][SSE] Regenerate odd sized sext/zext testsSimon Pilgrim2018-03-011-10/+158
| | | | llvm-svn: 326484
* AMDGPU/GlobalISel: Use a more correct getValueMappingMatt Arsenault2018-03-011-19/+56
| | | | | | | | | This was finding the wrong size registers for anything with more than 2 components. Patch by Tom Stellard llvm-svn: 326483
* AMDGPU/GlobalISel: Define instruction mapping for G_BITCASTMatt Arsenault2018-03-012-0/+37
| | | | | | Patch by Tom Stellard llvm-svn: 326482
* AMDGPU/GlobalISel: Mark i32->i64 zext as legalMatt Arsenault2018-03-012-0/+17
| | | | llvm-svn: 326481
* [AArch64] Add support for secrel add/load/store relocations for COFFMartin Storsjo2018-03-017-4/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D43288 llvm-svn: 326480
* AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.comprMatt Arsenault2018-03-012-4/+83
| | | | | | Patch by Tom Stellard llvm-svn: 326479
* [MinGW] Fix --{start,end}-group.Rui Ueyama2018-03-012-2/+4
| | | | | | | | Currently --start-group=foo is accidentally accepted by the MinGW driver. Differential Revision: https://reviews.llvm.org/D43836 llvm-svn: 326478
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.expMatt Arsenault2018-03-012-1/+98
| | | | | | Patch by Tom Stellard llvm-svn: 326477
* [RecordLayout] Only assert that fundamental type sizes are power of two on MSVCMartin Storsjo2018-03-013-4/+47
| | | | | | | | | | Make types with sizes that aren't a power of two an error (that can be disabled) in structs with ms_struct layout, except on mingw where the situation is quite likely to occur and GCC handles it silently. Differential Revision: https://reviews.llvm.org/D43908 llvm-svn: 326476
* [SimplifyLibCalls] Update an obviously copy and pasted header comment to ↵Craig Topper2018-03-011-4/+2
| | | | | | match this file. NFC llvm-svn: 326475
* [InstCombine] Auto-generate complete checks. NFCCraig Topper2018-03-011-141/+246
| | | | llvm-svn: 326474
* AMDGPU/GlobalISel: Define InstrMappings for G_ICMPMatt Arsenault2018-03-015-15/+168
| | | | | | Patch by Tom Stellard llvm-svn: 326472
* AMDGPU/GlobalISel: Make i32 mul legalMatt Arsenault2018-03-012-0/+19
| | | | llvm-svn: 326471
* AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEFMatt Arsenault2018-03-013-6/+35
| | | | | | Patch by Tom Stellard llvm-svn: 326470
* Driver: hoist `-fno-rtti-data` to a driver flagSaleem Abdulrasool2018-03-013-2/+4
| | | | | | | | This is needed for building with the GNU driver (`clang++`) when targeting Windows and using msvcprt. This flag is the equivalent of `/GR-`. llvm-svn: 326469
* AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANTMatt Arsenault2018-03-012-0/+32
| | | | | | Patch by Tom Stellard llvm-svn: 326468
* AMDGPU/GlobalISel: Add copyCost for VGPR->SGPR copiesMatt Arsenault2018-03-011-4/+7
| | | | | | Patch by Tom Stellard llvm-svn: 326467
* AMDGPU/GlobalISel: Make i32 xor legalMatt Arsenault2018-03-012-2/+20
| | | | llvm-svn: 326466
* AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legalMatt Arsenault2018-03-012-0/+39
| | | | | | Patch by Tom Stellard llvm-svn: 326465
* AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legalMatt Arsenault2018-03-012-0/+17
| | | | | | Patch by Tom Stellard llvm-svn: 326464
* Correct man page description for --section-startEd Maste2018-03-011-1/+1
| | | | | | | | | The argument is section=address, not just address. (For compatibility with GNU linkers we need to, but do not yet, accept --section-start=section=address.) llvm-svn: 326463
* [analyzer] Enable cfg-temporary-dtors by default.Artem Dergachev2018-03-017-11/+12
| | | | | | | | | | | | Don't enable c++-temp-dtor-inlining by default yet, due to this reference counting pointe problem. Otherwise the new mode seems stable and allows us to incrementally fix C++ problems in much less hacky ways. Differential Revision: https://reviews.llvm.org/D43804 llvm-svn: 326461
* [WebAssembly] Fix broken gcc build after rL326454Sam Clegg2018-03-013-13/+14
| | | | | | | The gcc builders were broken by rL326454 See: https://reviews.llvm.org/D43921 llvm-svn: 326460
* Where possible use --long-opt=value in lld man pageEd Maste2018-03-011-20/+20
| | | | | | | | | | | | | | We intend to maintain compatibility with GNU ld, and in the GNU world long options are conventionally specified as --long-option=value. For whatever reason GNU ld.bfd accepts both --long-option value and --long-option=value, but documents the former. Follow suit. Some lld long options do not accept the = form; this is probably a bug to be fixed (along with a man page update). Reported by Ingo Schwarze, for --entry. llvm-svn: 326459
* [clangd] Make symbol name a required parameter for CanonicalIncludes::mapHeaderEric Liu2018-03-012-10/+6
| | | | llvm-svn: 326458
* [NVPTX] use pattern matching to lower int_nvvm_match_all_sync*.Artem Belevich2018-03-013-43/+4
| | | | | | | | | Now that patterns can handle intrinsics returning multiple results, use tablegen'ed pattern matching instead of custom lowering. Differential Revision: https://reviews.llvm.org/D43890 llvm-svn: 326457
* [clangd] Support include canonicalization in symbol leve.Eric Liu2018-03-014-9/+105
| | | | | | | | | | | | | | | | | Summary: Symbols with different canonical includes might be defined in the same header (e.g. symbols defined in STL <iosfwd>). This patch adds support for mapping from qualified symbol names to canonical headers and special mapping for symbols in <iosfwd> Reviewers: sammccall, hokein Reviewed By: sammccall Subscribers: klimek, ilya-biryukov, jkorous-apple, cfe-commits Differential Revision: https://reviews.llvm.org/D43869 llvm-svn: 326456
* [WebAssembly] Use uint8_t for single byte values to match the specSam Clegg2018-03-013-12/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D43922 llvm-svn: 326455
* [WebAssembly] Use uint8_t for single byte values to match the specSam Clegg2018-03-017-87/+75
| | | | | | | | | | | | | The original BinaryEncoding.md document used to specify that these values were `varint7`, but the official spec lists them explicitly as single byte values and not LEB. A similar change for wabt is in flight: https://github.com/WebAssembly/wabt/pull/782 Differential Revision: https://reviews.llvm.org/D43921 llvm-svn: 326454
* [PDB] Defer writing the build id until the rest of the PDB is written.Zachary Turner2018-03-014-11/+32
| | | | | | | | | | For now this is NFC, but this small refactor opens the door to letting us embed a hash of the PDB in the build id field of the PDB. Differential Revision: https://reviews.llvm.org/D43913 llvm-svn: 326453
* [clangd] Forward all environment variables along with CLANGD_TRACE to clangd.Eric Liu2018-03-011-2/+4
| | | | llvm-svn: 326452
* [AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not foundAlexander Timofeev2018-03-011-1/+7
| | | | | | Differential revision: https://reviews.llvm.org./D43334 llvm-svn: 326451
* [Hexagon] Add guest registersKrzysztof Parzyszek2018-03-016-1/+301
| | | | llvm-svn: 326450
* Make TestDynamicValueSameBase gcc-compatiblePavel Labath2018-03-011-3/+7
| | | | | | | | | | gcc will say that the type of "this" is "T * const", clang "T *". Compare the unqualified type names to erase the difference between the two, as the constness is not a part of this test. FWIW, I think that the gcc behavior makes more sense here. llvm-svn: 326449
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