| Commit message (Collapse) | Author | Age | Files | Lines |
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retainable ObjC pointers without requiring a bridge-cast
by recognizing this as a +0 context. // rdar://16627903
llvm-svn: 211234
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This required untangling a mess of headers that included around.
This a recommit of r210953 with a fix for the removed accessor
for JITInfo.
llvm-svn: 211233
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llvm-svn: 211231
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fat files containing archives.
Also fix a bug in MachOUniversalBinary::ObjectForArch::ObjectForArch()
where it needed a >= when comparing the Index with the number of
objects in a fat file. As the index starts at 0.
llvm-svn: 211230
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The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.
llvm-svn: 211229
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This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.
Reviewed-by: Tom Stellard
llvm-svn: 211228
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Relax the tests to allow for differences between release and debug builds. This
should fix the buildbots.
Thanks to Benjamin Kramer and Eric Christo for their invaluable tip that this
was release build specific issue.
llvm-svn: 211227
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This hopefully fixes Windows
llvm-svn: 211225
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llvm-svn: 211224
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This patch enables clang to generate calls to __RTtypeid when lowering
typeid on win32 targets. Test cases are included.
llvm-svn: 211223
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llvm-svn: 211222
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We can delete the objects earlier now that we are copying the names to a buffer.
llvm-svn: 211221
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Fixes macros with varargs if the macro instantiation has a trailing comment.
Patch by Janne Grunau!
llvm-svn: 211219
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Patch by Janne Grunau!
llvm-svn: 211218
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Add support for _InterlockedCompareExchangePointer, _InterlockExchangePointer,
_InterlockExchange. These are available as a compiler intrinsic on ARM and x86.
These are used directly by the Windows SDK headers without use of the intrin
header.
llvm-svn: 211216
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boxed expression. // rdar://16417427
llvm-svn: 211215
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This change has a bit of a trickle down effect due to the fact that
there are a number of derived implementations of ExecutionEngine,
and that the mutex is not tightly encapsulated so is used by other
classes directly.
Reviewed by: rnk
Differential Revision: http://reviews.llvm.org/D4196
llvm-svn: 211214
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LLVMGetBitcodeModuleInContext should not take ownership on error. I will
try to localize this odd api requirement, but this should get the bots green.
llvm-svn: 211213
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The compiler, when JIT'ing code, can emit illegal DWARF line tables (address is line table sequences must increase). This changes fixes that issue by replacing previous line entries whose start address is the same with the new line entry to avoid having multiple line entries with the same address. Since the address range of lines entries is determined by the delta between the current and next line entry, this shouldn't cause any issues.
llvm-svn: 211212
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Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 211211
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Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 211210
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Doing this caused us to mistakenly think we'd seen a particular state before
when we actually hadn't, which resulted in false negatives. Credit to
Rafael Auler for discovering this issue!
llvm-svn: 211209
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Thanks to David Majnemer for noticing.
llvm-svn: 211208
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The main point of this class is to provide a cheap object interface to a bitcode
file, so it has to be as lazy as possible.
llvm-svn: 211207
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This reverts commit r211166. It broke public mac os x bots.
llvm-svn: 211206
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We do have use cases for the bitcode reader owning the buffer or not, but we
always know which one we have when we construct it.
It might be possible to simplify this further, but this is a step in the
right direction.
llvm-svn: 211205
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When emitting optimization remarks, we test for the presence of
instruction locations by testing for a valid llvm.dbg.cu annotation.
This is slightly inefficient because we can simply ask whether the
debug location we have is known or not.
Additionally, if my current plan works, I will need to remove the
llvm.dbg.cu annotation from the IL (or prevent it from being generated)
when -Rpass is used without -g. In those cases, we'll want to generate
line tables but we will want to prevent code generation from emitting
DWARF code for them.
Tested on x86_64.
llvm-svn: 211204
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When looking at the 64-bit SVR4 indirect call sequence, I noticed
an unnecessary load of r12. And indeed the code says:
// R12 must contain the address of an indirect callee.
But this is not correct; in the 64-bit SVR4 (ELFv1) ABI, there is
no need to load r12 at this point. It seems this code and comment
is a remnant of code originally shared with the Darwin ABI ...
This patch simply removes the unnecessary load.
llvm-svn: 211203
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Patch by John Wolf!
llvm-svn: 211202
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llvm-svn: 211201
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launches using the --forward-env or -F:
% ./debugserver --forward-env localhost:1234 -- /bin/ls
% ./debugserver -F localhost:1234 -- /bin/ls
Also allow new environment variables to be set using the "--env" or "-e":
% ./debugserver --env FOO=1 --env BAR=2 localhost:1234 -- /bin/ls
% ./debugserver -e FOO=1 -e BAR=2 localhost:1234 -- /bin/ls
<rdar://problem/17350654>
llvm-svn: 211200
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These deleted definitions had the wrong types.
Patch by Alex L!
llvm-svn: 211199
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ARMTargetStreamer implements ConstantPool and AssmeblerConstantPools
to keep track of assembler-generated constant pools that are used for
ldr-pseudo.
When implementing ldr-pseudo for AArch64, these two classes can be reused.
So this patch factors them out from ARM target to the general MC lib.
llvm-svn: 211198
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llvm-svn: 211197
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llvm-svn: 211196
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to forward class declarations for diagnosis.
// rdar://16681279
llvm-svn: 211195
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Move fp64 fceil tests to fceil64.ll
v2: rebase
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211194
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During an indirect function call sequence on the 64-bit SVR4 ABI,
generate code must load and then restore the TOC register.
This does not use a regular LOAD instruction since the TOC
register r2 is marked as reserved. Instead, the are two
special instruction patterns:
let RST = 2, DS = 2 in
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
"ld 2, 8($reg)", IIC_LdStLD,
[(PPCload_toc i64:$reg)]>, isPPC64;
let RST = 2, DS = 10, RA = 1 in
def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
"ld 2, 40(1)", IIC_LdStLD,
[(PPCtoc_restore)]>, isPPC64;
Note that these not only restrict the destination of the
load to r2, but they also restrict the *source* of the
load to particular address combinations. The latter is
a problem when we want to support the ELFv2 ABI, since
there the TOC save slot is no longer at 40(1).
This patch replaces those two instructions with a single
instruction pattern that only hard-codes r2 as destination,
but supports generic addresses as source. This will allow
supporting the ELFv2 ABI, and also helps generate more
efficient code for calls to absolute addresses (allowing
simplification of the ppc64-calls.ll test case).
llvm-svn: 211193
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Apparently C++ doesn't really have hex floating point constants.
llvm-svn: 211192
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No functionality change.
llvm-svn: 211191
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As requested by Hal Finkel, this adds back a test for calls to
a known-constant function pointer value, and verifies that the
64-bit SVR4 indirect function call sequence is used.
llvm-svn: 211190
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Patch by Ehsan Akhgari!
(Tiny tweak by me: renamed PathSegment to LibDir.)
Differential Revision: http://reviews.llvm.org/D4192
llvm-svn: 211189
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llvm-svn: 211188
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llvm-svn: 211187
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Copy what is done for 32-bit already so the order is about the same.
llvm-svn: 211186
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but SYNC with an implied operand ($stype = 0) is valid since Mips2.
llvm-svn: 211185
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llvm-svn: 211184
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CI has instructions for these, so this fixes them for older hardware.
llvm-svn: 211183
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llvm-svn: 211182
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This should be a source modifier, but this unblocks
most of my math patches.
llvm-svn: 211181
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