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* [GlobalISel|ARM] : Allow legalizing G_FSUBJaved Absar2017-10-307-8/+238
| | | | | | | | Adding support for VSUB. Reviewed by: @rovka Differential Revision: https://reviews.llvm.org/D39261 llvm-svn: 316902
* [analyzer] Use the signature of the primary template for issue hash calculationGabor Horvath2017-10-303-6/+17
| | | | | | | | | | | | | Now when a template is instantiated more times and there is a bug found in the instantiations the issue hash will be different for each instantiation even if every other property of the bug (path, message, location) is the same. This patch aims to resolve this issue. Note that explicit specializations still generate different hashes but that is intended. Differential Revision: https://reviews.llvm.org/D38728 llvm-svn: 316900
* [analyzer] Make issue hash related tests more conciseGabor Horvath2017-10-305-2531/+125
| | | | | | | | | | Extend ExprInspection checker to make it possible to dump the issue hash of arbitrary expressions. This change makes it possible to make issue hash related tests more concise and also makes debugging issue hash related problems easier. Differential Revision: https://reviews.llvm.org/D38844 llvm-svn: 316899
* Invalid used of 'w' suffix on push and pop using 64-bit register.Andrew V. Tischenko2017-10-302-5/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D38626 llvm-svn: 316898
* [ARM GlobalISel] Fixup r316572. NFCDiana Picus2017-10-301-9/+0
| | | | | | Just missed a few spots... llvm-svn: 316897
* [CodeGen] Generate TBAA info for reference loadsIvan A. Kosarev2017-10-306-72/+84
| | | | | | Differential Revision: https://reviews.llvm.org/D39177 llvm-svn: 316896
* [refactor] Fix a clang-tidy warning.Haojian Wu2017-10-301-1/+2
| | | | | | NFC llvm-svn: 316895
* Revert "[X86][AVX512] Adding a pattern for broadcastm intrinsic."Jina Nahias2017-10-302-73/+57
| | | | | | | This reverts commit r316890. Change-Id: I683cceee9848ef309b452293086b1f26a941950d llvm-svn: 316894
* [ELF] - Stop sorting input sections in createSections().George Rimar2017-10-302-32/+33
| | | | | | | | | | It does not seem that createSections() is a good place for applying sorting. Patch changes code to do that inside sortSections(), which looks more appropriate place. Differential revision: https://reviews.llvm.org/D39371 llvm-svn: 316893
* [analyzer] lock_guard and unique_lock extension for BlockInCriticalSection ↵Gabor Horvath2017-10-302-11/+85
| | | | | | | | | | checker A patch by zdtorok (Zoltán Dániel Török)! Differential Revision: https://reviews.llvm.org/D33729 llvm-svn: 316892
* Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.Florian Hahn2017-10-302-7/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version of the patch includes a fix addressing a stage2 LTO buildbot failure and addressed some additional nits. Original commit message: This updates the SCCP solver to use of the ValueElement lattice for parameters, which provides integer range information. The range information is used to remove unneeded icmp instructions. For the following function, f() can be optimized to ret i32 2 with this change source_filename = "sccp.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind readnone uwtable define i32 @main() local_unnamed_addr #0 { entry: %call = tail call fastcc i32 @f(i32 1) %call1 = tail call fastcc i32 @f(i32 47) %add3 = add nsw i32 %call, %call1 ret i32 %add3 } ; Function Attrs: noinline norecurse nounwind readnone uwtable define internal fastcc i32 @f(i32 %x) unnamed_addr #1 { entry: %c1 = icmp sle i32 %x, 100 %cmp = icmp sgt i32 %x, 300 %. = select i1 %cmp, i32 1, i32 2 ret i32 %. } attributes #1 = { noinline } Reviewers: davide, sanjoy, efriedma, dberlin Reviewed By: davide, dberlin Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D36656 llvm-svn: 316891
* [X86][AVX512] Adding a pattern for broadcastm intrinsic.Jina Nahias2017-10-302-57/+73
| | | | | | | Differential Revision: https://reviews.llvm.org/D38312 Change-Id: I6551fb13879e098aed74de410e29815cf37d9ab5 llvm-svn: 316890
* [IRCE][NFC] Store Length as SCEV in RangeCheck instead of ValueMax Kazantsev2017-10-302-7/+7
| | | | llvm-svn: 316889
* Revert r316887 to fix buildbot failures.Florian Hahn2017-10-302-228/+7
| | | | llvm-svn: 316888
* Recommit r315288: [SCCP] Propagate integer range info for parameters in IPSCCP.Florian Hahn2017-10-302-7/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version of the patch includes a fix addressing a stage2 LTO buildbot failure and addressed some additional nits. Original commit message: This updates the SCCP solver to use of the ValueElement lattice for parameters, which provides integer range information. The range information is used to remove unneeded icmp instructions. For the following function, f() can be optimized to ret i32 2 with this change source_filename = "sccp.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: norecurse nounwind readnone uwtable define i32 @main() local_unnamed_addr #0 { entry: %call = tail call fastcc i32 @f(i32 1) %call1 = tail call fastcc i32 @f(i32 47) %add3 = add nsw i32 %call, %call1 ret i32 %add3 } ; Function Attrs: noinline norecurse nounwind readnone uwtable define internal fastcc i32 @f(i32 %x) unnamed_addr #1 { entry: %c1 = icmp sle i32 %x, 100 %cmp = icmp sgt i32 %x, 300 %. = select i1 %cmp, i32 1, i32 2 ret i32 %. } attributes #1 = { noinline } Reviewers: davide, sanjoy, efriedma, dberlin Reviewed By: davide, dberlin Subscribers: mcrosier, gberry, mssimpso, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D36656 llvm-svn: 316887
* Add missing expected-no-diagnostics comment to test.Gabor Horvath2017-10-301-0/+1
| | | | llvm-svn: 316886
* [analyzer] Handle ObjC messages conservatively in CallDescriptionGabor Horvath2017-10-302-1/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D37470 llvm-svn: 316885
* [GVN][NFC] Mark instruction for deletion instead of immediate erasing in LoadPREMax Kazantsev2017-10-301-2/+1
| | | | | | | | It is done to uniformly handle instructions removal. Differential Revision: https://reviews.llvm.org/D39369 llvm-svn: 316884
* [X86] Rearrange code in X86InstrInfo.cpp to put all the ↵Craig Topper2017-10-301-270/+270
| | | | | | | | foldMemoryOperandImpl methods together without partial/undef register handling in the middle. NFC I have a future patch that wants to make use of the one of the partial functions in one of the earlier memory folding methods and the current ordering prevents that. llvm-svn: 316883
* [X86] Simplify code by removing an unnecessary temporary variable. NFCCraig Topper2017-10-301-2/+1
| | | | llvm-svn: 316882
* [X86] Move some EVEX->VEX code to a helper function to prepare for a future ↵Craig Topper2017-10-301-24/+33
| | | | | | patch. NFC llvm-svn: 316881
* Remove unnecessary code.Rui Ueyama2017-10-291-6/+3
| | | | | | | Discarded section's Repl always points to itself, so returning Sec is not different from returning Sec->Repl. llvm-svn: 316880
* Move "Assigned" bit from SectionBase to InputSectionBase.Rui Ueyama2017-10-291-14/+14
| | | | | | | | | This bit is to manage whether an input section has already been assigned to some output section by linker scripts or not. So it logically belongs to InputSectionBase. SectionBase is a common base class for input and output sections, so that wasn't the right place to define the bit. llvm-svn: 316879
* Remove an obscure comment.Rui Ueyama2017-10-291-4/+1
| | | | llvm-svn: 316878
* ELF: Correctly set edata if there are no .bss sections.Peter Collingbourne2017-10-292-20/+35
| | | | | | | | | | | edata needs to be set to the end of the last mapped initialized section. We were previously mishandling the case where there were no non-mapped sections by setting it to the end of the last section in the output file. Differential Revision: https://reviews.llvm.org/D39399 llvm-svn: 316877
* Initialize members not by assignment but by the member initializer list.Rui Ueyama2017-10-291-9/+4
| | | | llvm-svn: 316876
* [SelectionDAG] Add SEXT/AND/XOR/Or demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-292-30/+26
| | | | llvm-svn: 316875
* Initial triageMarshall Clow2017-10-291-16/+16
| | | | llvm-svn: 316874
* Update status of 2950Marshall Clow2017-10-291-4/+4
| | | | llvm-svn: 316873
* [Acc] Do not statically dispatch into IslNodeBuilder's createForPhilip Pfaffe2017-10-293-9/+14
| | | | | | | | | | | | | | | | | | | | Summary: When GPUNodeBuilder creates loops inside the kernel, it dispatches to IslNodeBuilder. This however is surprisingly dangerous, since it accesses the AST Node's user through the wrong type. This patch fixes this problem by overriding createFor correctly. This fixes PR35010. Reviewers: grosser, bollu, Meinersbur Reviewed By: Meinersbur Subscribers: Meinersbur, nemanjai, pollydev, llvm-commits, kbarton Differential Revision: https://reviews.llvm.org/D39364 llvm-svn: 316872
* [X86][SSE] Split ComputeNumSignBits SEXT/AND/XOR/OR demandedelts testSimon Pilgrim2017-10-291-17/+65
| | | | | | Max depth was being exceeded which could prevent some combines working llvm-svn: 316871
* Fix two testcases. NFC intended.Philip Pfaffe2017-10-292-13/+13
| | | | | | | | Add missing %loadPolly directive to support out of tree builds. One of the changes is somewhat bigger, because the directive turns on LLVM names, and the testcase deosn't use those. llvm-svn: 316870
* [(new) Pass Manager] instantiate SimplifyCFG with the same options as the old PMSanjay Patel2017-10-293-64/+40
| | | | | | | | | | | | The old PM sets the options of what used to be known as "latesimplifycfg" on the instantiation after the vectorizers have run, so that's what we'redoing here. FWIW, there's a later SimplifyCFGPass instantiation in both PMs where we do not set the "late" options. I'm not sure if that's intentional or not. Differential Revision: https://reviews.llvm.org/D39407 llvm-svn: 316869
* [X86][SSE] ComputeNumSignBits tests showing missing SEXT/AND/XOR/OR ↵Simon Pilgrim2017-10-291-0/+68
| | | | | | demandedelts support llvm-svn: 316868
* Issues to be voted on in ABQMarshall Clow2017-10-291-31/+50
| | | | llvm-svn: 316867
* [SelectionDAG] Add SRA/SHL demanded elts support to ComputeNumSignBitsSimon Pilgrim2017-10-292-27/+43
| | | | | | Introduce a isConstOrDemandedConstSplat helper function that can recognise a constant splat build vector for at least the demanded elts we care about. llvm-svn: 316866
* [X86][SSE] ComputeNumSignBits tests showing missing SHL/SRA demandedelts ↵Simon Pilgrim2017-10-291-3/+90
| | | | | | support llvm-svn: 316865
* [X86] Add a slow-incdec command line to atomic-eflags-reuse.llCraig Topper2017-10-291-38/+82
| | | | | | I believe the test_sub_1_cmp_1_setcc_ugt test case is being miscompiled in the fast inc/dec case. llvm-svn: 316864
* Fix ubsan error that shift amount 64 is too large.Rui Ueyama2017-10-291-1/+3
| | | | llvm-svn: 316863
* Remove a redundant temporary variable.Rui Ueyama2017-10-291-2/+1
| | | | llvm-svn: 316862
* [X86] Remove combine that turns X86ISD::LSUB into X86ISD::LADD. Update ↵Craig Topper2017-10-293-32/+11
| | | | | | | | | | | | patterns that depended on this. If the carry flag is being used, this transformation isn't safe. This does prevent some test cases from using DEC now, but I'll try to look into that separately. Fixes PR35068. llvm-svn: 316860
* [X86] Fix typo in comment. NFCCraig Topper2017-10-291-1/+1
| | | | llvm-svn: 316859
* Driver: default to `unsigned int` `wchar_t` for ARMSaleem Abdulrasool2017-10-292-1/+59
| | | | | | | | | | AAPCS and AAPCS64 mandate that `wchar_t` with `-fno-short-wchar` is an `unsigned int` rather than a `signed int`. Ensure that the driver does not flip the signedness of `wchar_t` for those targets. Add additional tests to ensure that this does not regress. llvm-svn: 316858
* [X86] Use the extended vector register classes in fast isel with AVX512F/VL.Craig Topper2017-10-291-10/+10
| | | | llvm-svn: 316857
* [X86] Add AVX512 support to X86FastISel::X86SelectFPExt and ↵Craig Topper2017-10-292-4/+13
| | | | | | X86FastISel::X86SelectFPTrunc. llvm-svn: 316856
* [X86] Use update_llc_test_checks.py to regenerate ↵Craig Topper2017-10-291-16/+37
| | | | | | fast-isel-int-float-conversion.ll llvm-svn: 316855
* [X86] Use update_llc_test_checks.py to regenerate fast-isel-fptrunc-fpext.llCraig Topper2017-10-291-18/+39
| | | | llvm-svn: 316854
* [X86] Add AVX512 support to X86FastISel::X86MaterializeFPCraig Topper2017-10-292-2/+8
| | | | llvm-svn: 316853
* [analyzer] MisusedMovedObjectChecker: More precise warning messagePeter Szecsi2017-10-282-20/+66
| | | | | | | | | | | | Added new enum in order to differentiate the warning messages on "misusing" into 3 categories: function calls, moving an object, copying an object. (At the moment the checker gives the same message in case of copying and moving.) Additional test cases added as well. Differential Revision: https://reviews.llvm.org/D38674 llvm-svn: 316852
* [X86] Remove invalid code from LowerVSELECT.Craig Topper2017-10-281-4/+0
| | | | | | | | This code attempted to say that v8i16/v16i16 VSELECT is legal if BWI and VLX are enabled, but the only way we could reach this point is if the condition was not a vXi1 type. Which means it really wasn't legal. We don't have any tests that exercise this code. So I'm hoping it wasn't really reachable. llvm-svn: 316851
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