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| author | Craig Topper <craig.topper@intel.com> | 2017-10-29 02:50:31 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-29 02:50:31 +0000 |
| commit | 5f2289a13ca32cbfd5250f12876f020248eb771b (patch) | |
| tree | 74b52fa22a38f7e659b6afe68f841f7783d7d52e | |
| parent | 8373336a22212b35ca1a307f21febdd242ba7459 (diff) | |
| download | bcm5719-llvm-5f2289a13ca32cbfd5250f12876f020248eb771b.tar.gz bcm5719-llvm-5f2289a13ca32cbfd5250f12876f020248eb771b.zip | |
[X86] Add AVX512 support to X86FastISel::X86SelectFPExt and X86FastISel::X86SelectFPTrunc.
llvm-svn: 316856
| -rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll | 1 |
2 files changed, 13 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 4c8decaf591..84264020dac 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -2473,9 +2473,13 @@ bool X86FastISel::X86SelectFPExtOrFPTrunc(const Instruction *I, bool X86FastISel::X86SelectFPExt(const Instruction *I) { if (X86ScalarSSEf64 && I->getType()->isDoubleTy() && I->getOperand(0)->getType()->isFloatTy()) { + bool HasAVX512 = Subtarget->hasAVX512(); // fpext from float to double. - unsigned Opc = Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; - return X86SelectFPExtOrFPTrunc(I, Opc, &X86::FR64RegClass); + unsigned Opc = + HasAVX512 ? X86::VCVTSS2SDZrr + : Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; + return X86SelectFPExtOrFPTrunc( + I, Opc, HasAVX512 ? &X86::FR64XRegClass : &X86::FR64RegClass); } return false; @@ -2484,9 +2488,13 @@ bool X86FastISel::X86SelectFPExt(const Instruction *I) { bool X86FastISel::X86SelectFPTrunc(const Instruction *I) { if (X86ScalarSSEf64 && I->getType()->isFloatTy() && I->getOperand(0)->getType()->isDoubleTy()) { + bool HasAVX512 = Subtarget->hasAVX512(); // fptrunc from double to float. - unsigned Opc = Subtarget->hasAVX() ? X86::VCVTSD2SSrr : X86::CVTSD2SSrr; - return X86SelectFPExtOrFPTrunc(I, Opc, &X86::FR32RegClass); + unsigned Opc = + HasAVX512 ? X86::VCVTSD2SSZrr + : Subtarget->hasAVX() ? X86::VCVTSD2SSrr : X86::CVTSD2SSrr; + return X86SelectFPExtOrFPTrunc( + I, Opc, HasAVX512 ? &X86::FR32XRegClass : &X86::FR32RegClass); } return false; diff --git a/llvm/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll b/llvm/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll index 0614a0e40a4..1035c256790 100644 --- a/llvm/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll +++ b/llvm/test/CodeGen/X86/fast-isel-fptrunc-fpext.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=ALL --check-prefix=AVX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=ALL --check-prefix=AVX ; ; Verify that fast-isel doesn't select legacy SSE instructions on targets that ; feature AVX. |
